Memory Module, Memory System, and Inforamtion Device

ABSTRACT

A memory system including ROM and RAM in which reading and writing are enabled. A memory system includes a non-volatile memory (FLASH), DRAM, a control circuit, and an information processing device. Data in FLASH is transferred to SRAM or DRAM in advance. Data transfer between the non-volatile memory and the DRAM can be performed in the background. The memory system including these plural chips is configured as a memory system module in which each chip is mutually laminated and each chip is wired via a ball grid array (BGA) and bonding wire between the chips. Data in FLASH can be read at the similar speed to that of DRAM by securing a region in which the data in FLASH can be copied in DRAM and transferring the data to DRAM in advance immediately after power is turned on or by a load instruction.

TECHNICAL FIELD

The present invention relates to a memory system including a dynamicrandom access memory (DRAM) and a method of controlling the memorysystem.

BACKGROUND ART

Heretofore, a stacked memory acquired by integrally molding a flashmemory having 32-Mbit capacity and a static random access memory (SRAM)having 4-Mbit capacity in a fine pitch ball grid array (FBGA) typepackage in the form of a stacked chip has been provided. As for theflash memory and SRAM, the respective address input terminals and therespective data input/output terminals are connected to an input/outputelectrode of the FBGA type package in common. However, each controlterminal is independent (for example, refer to “a stacked memory(stacked CSP) a flash memory+a RAM. data sheet)”, type name LRS1380,[online], Dec. 10, 2001, Sharp Corporation, searched on Aug. 21, 2002,URL:http://www.sharp.co.jp/products/device/flash/cmlist.ht ml).

There is also a stacked memory acquired by integrally molding a flashmemory chip and a DRAM chip in a lead frame type package. In the stackedmemory, respective address input terminals, respective data input/outputterminals and respective control terminals of the flash memory and DRAMare connected to an input/output electrode of the package in common (forexample, see FIGS. 1 and 17 in Japanese Patent Laid-Open No. H5(1993)-299616 and refer to a specification of an European patentapplication No. 0566306).

There is also a system configured by a flash memory treated as a mainmemory device, a cache memory, a controller and CPU (for example, seeFIG. 1 in Japanese Patent Laid-Open No. H7 (1995)-146820).

There is also a semiconductor memory configured by a flash memory, DRAMand a transfer control circuit (for example, see FIG. 2 inJP-A-2001-5723).

DISCLOSURE OF THE INVENTION

Inventors of the invention examined a mobile telephone, a memory moduleused for the mobile telephone in which a flash memory and SRAM werepackaged in one package and the operation prior to the invention.

As shown in FIG. 32, currently, an information processing device PRC anda memory module MCM are used in a mobile telephone.

The information processing device PRC is configured by a centralprocessing unit CPU and an SRAM controller. The memory module MCM isconfigured by a NOR flash memory NOR FLASH and SRAM. The informationprocessing device PRC accesses the memory module MCM via an SRAMinterface (SRAM IF) to read and write data.

After power is turned on, the information processing device PRC readsboot program data stored in the NOR flash memory NOR FLASH and activatesitself. Afterward, the information processing device PRC reads anapplication program from the NOR flash memory NOR FLASH if necessary andexecutes it in the central processing unit CPU. SRAM functions as a workmemory and stores the result of operation by the central processing unitCPU.

Recently, as functions (for distributing music and games) added to amobile telephone increase, applications, data and a work arearespectively managed by the mobile telephone increase and it isestimated that a flash memory and SRAM respectively having larger memorysize are required. Further, the enhancement of the functions of a recentmobile telephone is remarkable and a demand for a high-speed andlarge-capacity memory increases.

Currently, a NOR flash memory used in a mobile telephone uses a memoryarray system called NOR configuration. The NOR type denotes arrayconfiguration in which the parasitic resistance of a memory array isminimized and the resistance is reduced by providing a metal bit linecontact in the ratio of one to two memory cells connected in parallel.Therefore, the read time is approximately 80 ns and can be substantiallymade similar to the read time of SRAM. However, as one contact per twocells is required to be provided, there is a problem that the contactpart accounts for a large rate for the area of a chip, the area of a1-bit memory cell increases, and the NOR type cannot correspond to theincrease of capacity.

For a representative large-capacity flash memory, there are an AND flashmemory using AND configuration for a memory array and a NAND flashmemory using NAND configuration. As for these flash memories, as one bitline contact is provided to 16 to 128 pieces of cells, a high-densitymemory array can be implemented. Therefore, the area of a 1-bit memorycell can be reduced more than that of the NOR flash memory and the flashmemories can correspond to the increase of capacity. However, it isascertained that the read time until first data is output isapproximately 25 to 50 μs, is slow, and the flash memories lackconsistency with SRAM.

Then, one of the objects of the invention is to provide a memory systemincluding ROM and RAM which have large memory size and from/to whichdata can be read and written at high speed.

Representative means of the invention are as follows. An informationprocessing device, a flash memory, SRAM and DRAM configured by pluralmemory banks are packaged in one molded device, and an electrode forsupplying power to wiring of semiconductor chips and an electrode usedfor connecting the molded device and the outside of the molded deviceare provided to the molded device.

At this time, to speed up read time for a request for reading data inthe flash memory from the information processing device, a memorycontroller is connected to SRAM, DRAM and the flash memory, by thememory controller, data transfer from the flash memory to SRAM and datatransfer from SRAM to the flash memory are performed, and data transferfrom the flash memory to DRAM and data transfer from DRAM to the flashmemory are performed. It is desirable that after power is turned on andwhen a transfer instruction is issued, control that at least a part ofdata in the flash memory is transferred to SRAM and DRAM by the memorycontroller is made.

Control may be also made so that even while data transfer between theflash memory and DRAM is performed by the memory controller, access toDRAM from the information processing device for read or write isaccepted and data is read or written at high speed. It is desirable thatdata transfer between the flash memory and DRAM is performed in thebackground inside the semiconductor device.

Further, the memory controller also executes refresh control of DRAM indata transfer from the flash memory to DRAM after power is turned on. Inthe data transfer from the flash memory to DRAM, it is desirable thatcontrol is made so that DRAM is automatically refreshed, when the datatransfer is finished, DRAM is turned in a self-refresh condition andafterward, the self-refresh condition is released by a self-refreshrelease instruction from a device outside the semiconductor device.Control may be also made so that auto-refresh operation by the memorycontroller is stopped by an auto-refresh instruction from theinformation processing device.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram showing a memory system to which the inventionis applied;

FIG. 2 is an explanatory drawing showing one example of an address mapof the memory system to which the invention is applied;

FIG. 3 show one example of the operation when power is turned on of thememory system to which the invention is applied;

FIG. 4 shows one example of the initialization when power is turned onof DRAM of the memory system to which the invention is applied;

FIG. 5 shows one example of the initialization when power is turned onof DRAM of a memory module to which the invention is applied;

FIG. 6 shows the flow of data transfer operation when power is turned onfrom FLASH to SRAM in the memory system to which the invention isapplied;

FIG. 7 shows the flow of data transfer operation when power is turned onfrom FLASH to DRAM in the memory system to which the invention isapplied;

FIG. 8 is a flowchart showing the flow of data transfer operation fromFLASH to DRAM in the memory system according to the invention;

FIG. 9 is a flowchart showing the flow of data transfer operation fromDRAM to FLASH in the memory system according to the invention;

FIG. 10 is a flowchart showing the flow of data transfer operation fromFLASH to SRAM in the memory system according to the invention;

FIG. 11 is a flowchart showing the flow of data transfer operation fromSRAM to FLASH in the memory system according to the invention;

FIG. 12 is a block diagram showing one example of the configuration ofFLASH shown in FIG. 1;

FIG. 13 is a timing chart showing one example of reading data from FLASHshown in FIG. 1;

FIG. 14 is a block diagram showing the memory system to which theinvention is applied;

FIG. 15 is a block diagram showing one example of the configuration ofFLASH shown in FIG. 14;

FIG. 16 is a timing chart showing one example of reading data from FLASHshown in FIG. 14;

FIG. 17 is a block diagram showing a memory system to which theinvention is applied;

FIG. 18 is a block diagram showing a memory system to which theinvention is applied;

FIG. 19 is a block diagram showing one example of the configuration ofFLASH shown in FIG. 18;

FIG. 20 is a timing chart showing one example of reading data from FLASHshown in FIG. 18;

FIG. 21 is a block diagram showing a memory system to which theinvention is applied;

FIG. 22 is a block diagram showing a memory system to which theinvention is applied;

FIG. 23 is an explanatory drawing showing one example of an address mapof the memory system to which the invention is applied;

FIG. 24 is a block diagram showing a memory system to which theinvention is applied;

FIG. 25( a) and FIG. 25( b) show one embodiment of the memory systemaccording to the invention;

FIG. 26( a) and FIG. 26( b) show one embodiment of the memory systemaccording to the invention;

FIG. 27( a) and FIG. 27( b) show one embodiment of the memory systemaccording to the invention;

FIG. 28( a) and FIG. 28( b) show a transformed example of an embodimentof the memory system according to the invention;

FIGS. 29( a) and 29(b) show one embodiment of the memory systemaccording to the invention;

FIG. 30 is a block diagram showing an example of the configuration of amobile telephone utilizing the memory system according to the invention;

FIG. 31 is a block diagram showing an example of the configuration of amobile telephone utilizing the memory system according to the invention;and

FIG. 32 is a block diagram showing an example of the configuration of aconventional type memory utilized in a mobile telephone.

BEST MODE FOR CARRYING OUT THE INVENTION

Referring to the attached drawings, embodiments of the invention will bedescribed in detail below. In the embodiments, a circuit elementconfiguring each block is not particularly limited, however, it isformed on/over one semiconductor substrate made of monocrystallinesilicon for example by integrated circuit (well-known CMOS (acomplementary MOS transistor)) technology.

First Embodiment

FIG. 1 shows a memory system configured by an information processingdevice CHIP4 (MS) equivalent to a first embodiment to which theinvention is applied and a memory module MM. Each will be describedbelow.

The memory module MM includes CHIP1 (FLASH), CHIP2 (CTL_LOGIC) and CHIP3(DRAM).

CHIP1 (FLASH) is a non-volatile memory. For the non-volatile memory, aread only memory (ROM), electrically erasable and programmable ROM(EEPROM) and a flash memory can be used. This embodiment will bedescribed using a flash memory for an example.

Though the following are not particularly limited, a typicalnon-volatile memory used for CHIP1 (FLASH) is a large-capacity flashmemory equipped with an NAND interface (NAND IF), has large memory sizeof approximately 128 Mbits, its read time (time since a request forreading until data is output) is approximately 25 to 100 μs, and it isrelatively slow.

CHIP3 (DRAM) is a dynamic random access memory and has various typessuch as extended data out DRAM (EDO DRAM), synchronous DRAM (SDRAM) anda double data rate mode (a DDR mode) depending upon internalconfiguration and difference in an interface. Any DRAM can be used forthe memory module MM. This embodiment will be described using SDRAM foran example.

Though the following are not particularly limited, typical SDRAM usedfor CHIP3 (DRAM) has large memory size of approximately 256 Mbits andits read time is approximately 35 to 55 ns. CHIP2 (CTL_LOGIC) is acontrol circuit for controlling data transfer between CHIP1 (FLASH) andCHIP3 (DRAM) and between SRAM and CHIP3 (DRAM).

SRAM is a static random access memory and has various types such as anasynchronous static random access memory and a synchronous static randomaccess memory depending upon internal configuration and difference in aninterface. Any static random access memory can be used for the memorymodule MM, however, this embodiment will be described using anasynchronous static random access memory for an example. Though thefollowing are not particularly limited, the memory size of SRAM used inthis embodiment is approximately 64 kbits and its read time isapproximately 80 ns.

Data transfer between CHIP1 (FLASH) and CHIP2 (CTL_LOGIC) is performedvia a NAND interface (NAND IF) and data transfer between CHIP2(CTL_LOGIC) and CHIP3 (DRAM) is performed via an SDRAM interface (SDRAMIF).

The information processing device CHIP4 is configured by a centralprocessing unit CPU, an SRAM controller SRC and a DRAM controller SDC.The SRAM controller accesses SRAM. via an SRAM interface (SRAM IF) toread/write data. The DRAM controller accesses CHIP3 (DRAM) via CHIP2(CTL_LOGIC) and the SDRAM interface (SDRAM IF) to read/write data.

CHIP1 (FLASH) is divided into an initial program region and a main dataregion though they are not particularly limited. In the initial programregion, boot program data for activating the information processingdevice CHIP4 (MS) immediately after power is turned on, designation datafor an automatic data transfer region showing a data range in the maindata region to be transferred to SDRAM and refresh control select dataare stored.

CHIP3 (DRAM) is divided into a work region and a copy region though theyare not particularly limited, the work region is utilized for a workmemory when a program is executed, and the copy region is utilized for amemory for copying data from FLASH.

SRAM is divided into a boot region and a buffer region though they arenot particularly limited, the boot region is utilized for storing bootprogram data for activating the information processing device CHIP4(MS), and the buffer region is utilized for a buffer memory for datatransfer between CHIP1 (FLASH) and SRAM.

CHIP2 (CTL_LOGIC) is configured by a memory management unit MU, acommand/address generator CMAD, an access arbiter ARB, an initializecircuit INT, a refresh control circuit REF, a data buffer BUF, a controlregister SREG accessible via the SRAM interface (SRAM IF), a controlregister DREG accessible via the SDRAM interface, a flash controlcircuit FCON, an error detecting and correcting circuit ECC and anaddress replacement circuit REP.

Correspondence between an address of CHIP1 (FLASH) and an address in thecopy region of CHIP3 (DRAM), in the boot region and in the buffer regionrespectively of SRAM can be determined by the memory management unit MUof CHIP2 (CTL_LOGIC). For example, generally, CHIP3 (DRAM) is configuredby four memory banks (banks 0 to 3), though they are not particularlylimited, the copy region of CHIP3 (DRAM) can be allocated to the bank 0and the bank 1 by the memory management unit and the work region can bealso allocated to the bank 2 and the bank 3.

The operation of this memory system will be described below.

When power is applied to the information processing device CHIP4 (MS),CHIP3 (DRAM), CHIP2 (CTL_LOGIC) and CHIP1 (FLASH), the flash controlcircuit FCON reads data in the initial program region of CHIP1 (FLASH)and the error detecting and correcting circuit ECC checks whether thedata has an error or not. If the data has no error, the data is directlytransferred to SRAM and in case the data has an error, the error iscorrected and data after correction is transferred to SRAM. As describedabove, the information processing device CHIP4 (MS) reads boot programdata and can activate itself promptly by automatically transferring theboot program data from CHIP1 (FLASH) to SRAM immediately after power isturned on.

While the information processing device CHIP4 (MS) activates itself, theinitialize circuit INT executes a sequence for initializing CHIP3(DRAM). The flash control circuit FCON reads designation data for anautomatic data transfer region from SRAM, sequentially reads data in themain data region of CHIP1 (FLASH) in a range designated in the data, andthe error detecting and correcting circuit ECC checks whether the datahas an error or not. If the data has no error, the data is directlytransferred to the data buffer BUF, in case the data has an error, theerror is corrected, and data after correction is transferred to the databuffer BUF. The command/address generator CMAD sequentially transfersthe data held in the data buffer BUF to CHIP3 (DRAM). When data transferis started, the refresh control circuit REF issues an auto-refreshcommand to CHIP3 (DRAM) via the command/address generator CMAD to holddata in CHIP3 (DRAM). When the data transfer is finished, the accessarbiter writes a data transfer completion flag showing the completion ofdata transfer to the control register DREG.

The information processing device CHIP4 (MS) accesses the controlregister DREG via the SDRAM interface (SDRAM IF) and can know that datatransfer immediately after power is turned on is completed by readingthe data transfer completion flag in the control register DREG.

As CHIP3 (DRAM) has a characteristic that in case refresh operation isnot executed periodically, data held in a memory cell is lost, therefresh control circuit REF applies auto-refresh operation to CHIP3(DRAM) when data transfer from CHIP1 (FLASH) to CHIP3 (DRAM) when poweris turned on is started. Further, after the data transfer is completed,the refresh control circuit reads refresh control select data from SRAM.In case the refresh control select data is at a high level, the refreshcontrol circuit REF stops auto-refresh operation and data-hold byrefresh operation proceeds to control from the information processingdevice CHIP4 (MS) when an auto-refresh instruction or a self-refreshinstruction is input from the information processing device CHIP4 (MS)to CHIP2 (CTL_LOGIC).

Besides, in case the refresh control select data is at a low level, therefresh control circuit applies self-refresh operation to CHIP3 (DRAM)after data transfer is completed to hold data in CHIP3 (DRAM). In aself-refresh state, data can be held with lower power than normalauto-refresh operation. In the state of self-refreshment by the refreshcontrol circuit REF, when a self-refresh release instruction is inputfrom the information processing device CHIP4 (MS), the self-refreshstate is released and simultaneously, data-hold by refresh operationproceeds to control from the information processing device CHIP4 (MS).

As described above, the information processing device CHIP4 (MS) readsits boot program data by automatically transferring the boot programdata from CHIP1 (FLASH) to SRAM immediately after power is turned on andcan activate itself promptly. Further, as access to the memory module MMis enabled immediately when the information processing device CHIP4 (MS)is activatedby automatically transferring data in CHIP1 (FLASH) to CHIP3(DRAM) while the information processing device CHIP4 (MS) activatesitself, the performance can be enhanced.

Data transfer between CHIP1 (FLASH) and CHIP3 (DRAM) after anoperational sequence is finished when power is turned on is executedwhen the information processing device CHIP4 (MS) accesses the controlregister DREG and writes a load instruction code or a store instructioncode to it. Data in the main data region of CHIP1 (FLASH) can betransferred to the copy region of CHIP3 (DRAM) by the load instructionand data in the copy region of CHIP3 (DRAM) can be transferred to themain data region of CHIP1 (FLASH) by the store instruction.

When the information processing device CHIP4 (MS) writes a loadinstruction code, a load initiation address and transfer data size tothe control register DREG via the SDRAM interface (SDRAM IF), data fromthe load initiation address for the transfer data size out of data inCHIP1 (FLASH) is transferred to the copy region of CHIP3 (DRAM). First,the flash control circuit FCON sequentially reads data from CHIP1(FLASH). If data read from CHIP1 (FLASH) has no error, the data isdirectly transferred to the transfer data buffer BUF and in case thedata has an error, the error is corrected in the error detecting andcorrecting circuit ECC and data after correction is transferred to thetransfer data buffer BUF. The command/address generator CMADsequentially transfers data held in the data buffer BUF to CHIP3 (DRAM).

When the information processing device CHIP4 (MS) writes a loadinstruction code, a load initiation address and transfer data size tothe control register DREG via the SDRAM interface (SDRAM IF), data froma store initiation address for the transfer data size out of data in thecopy region of CHIP3 (DRAM) is transferred to CHIP1 (FLASH).

First, the command/address generator CMAD issues a read instruction andan address to CHIP3 (DRAM) via the SDRAM interface (SDRAM IF) to readdata.

Data read from CHIP3 (DRAM) is transferred to the data buffer BUF. Theflash control circuit FCON reads the data transferred to the data bufferBUF and writes it to CHIP1 (FLASH).

The address replacement circuit REP checks whether the writing succeedsor not and finishes processing if the writing succeeds. When the writingfails, the data is written to a new address for replacement prepared inCHIP1 (FLASH) in advance. When replacement is made, a defective addressand the information of the address with which the defective address isreplaced are held and managed.

In FIG. 1, the error detecting and correcting circuit ECC and theaddress replacement circuit REP are provided to the control circuitCHIP2 (CTL_LOGIC), however, needless to say, they may be also providedto CHIP1 (FLASH), CHIP1 (FLASH) may also correct an error and transferthe data to CHIP3 (DRAM) via the control circuit CHIP2 (CTL_LOGIC), mayalso replace an address of data transferred fromCHIP3 (DRAM) to CHIP1(FLASH) and the data may be also written.

Data transfer between CHIP1 (FLASH) and SRAM after an operationalsequence is finished when power is turned on is executed when theinformation processing device CHIP4 (MS) accesses the control registerSREG and writes a load instruction code or a store instruction code.Data in CHIP1 (FLASH) can be transferred to the buffer region of SRAM bythe load instruction and data in the buffer region of SRAM can betransferred to CHIP1 (FLASH) by the store instruction.

When the information processing device CHIP4 (MS) writes a loadinstruction, a load initiation address and transfer data size to thecontrol register SREG via the SRAM interface (SRAM IF), data in CHIP1(FLASH) from the load initiation address is read by the transfer datasize and is transferred to the buffer region of SRAM.

First, the flash control circuit FCON sequentially reads from CHIP1(FLASH). If data read from CHIP1 (FLASH) has no error, the data isdirectly transferred to the buffer region of SRAM and in case the datahas an error, the error is corrected in the error detecting andcorrecting circuit ECC and data after correction is transferred to thebuffer region of SRAM.

When the information processing device CHIP4 (MS) writes a storeinstruction code, a store initiation address and transfer data size tothe control register SREG via the SRAM interface (SRAM IF) in the sameway as data transfer between CHIP1 (FLASH) and SRAM by the loadinstruction, data in the buffer region of SRAM from the store initiationaddress for the transfer data size is written to CHIP1 (FLASH).

First, the flash control circuit FCON reads data in the buffer region ofSDRAM and writes the data to CHIP1 (FLASH).

The address replacement circuit REP checks whether the writing succeedsor not and if the writing succeeds, the circuit finishes the processing.When the writing fails, the address replacement circuit writes the datato a new address for replacement prepared in CHIP1 (FLASH) beforehand.When replacement is made, a defective address and the information of anaddress with which the defective address is replaced are held andmanaged.

As described above, as boot program data and designation data for anautomatic data transfer region are written to the initial program regionof FLASH via SRAM IF and the buffer region of SRAM and a booting methodand a data transfer region immediately after power is turned on can bechanged, flexible correspondence according to a request of a mobiledevice is enabled and the function can be enhanced.

In case the information processing device CHIP4 (MS) accesses the copyregion of CHIP3 (DRAM), it inputs an address for selecting the copyregion of CHIP3 (DRAM) and a read instruction or a write instruction toCHIP2 (CTL_LOGIC) via the SDRAM interface. Afterward, CHIP2 (CTL_LOGIC)reads or writes data from/to the copy region of CHIP3 (DRAM) accordingto the input instruction and the input address.

As described above, as data in CHIP1 (FLASH) is held in the copy regionof CHIP3 (DRAM), time for reading or writing the data in CHIP1 (FLASH)is equalized to that of DRAM by accessing CHIP3 (DRAM) and reading orwriting the data. Reading and writing from/to the work region of CHIP3(DRAM) are also executed according to the same procedure as the accessto the copy region.

In case the information processing device CHIP4 (MS) accesses SRAM, itinputs an address and a read instruction or a write instruction to SRAMvia the SDRAM interface. Afterward, SRAM reads or writes data accordingto this instruction and the address.

The information processing device CHIP4 (MS) thereby transfers data fromCHIP1 (FLASH) to SRAM immediately after power is turned on, reads heldboot program data, and can activate itself promptly. Further, as theinformation processing device CHIP4 (MS) can change a program in CHIP1(FLASH) via the buffer region of SRAM and can read and verify thecontents of a program, it can flexibly correspond to a request of amobile device.

Suppose that the copy region of CHIP3 (DRAM) is allocated to the bank 0and the bank 1 in the memory management unit MU and the work region isallocated to the bank 2 and the bank 3. In case access to the bank 3 ofCHIP3 (DRAM) is made via the SDRAM interface of the informationprocessing device CHIP4 (MS) when access to the bank 0 of CHIP3 (DRAM)is made by a load instruction or a store instruction, the controlcircuit CHIP2 (CTL_LOGIC) halts the access to CHIP3 (DRAM) by the loadinstruction or the store instruction and gives the access from theinformation processing device CHIP4 (MS) priority. When the access isfinished, the access by the load instruction or the store instruction isrestarted.

As described above, access from the information processing device CHIP4(MS) to CHIP3 (DRAM) is enabled even during data transfer between CHIP1(FLASH) and CHIP3 (DRAM) by the load instruction or the storeinstruction without being conscious of the data transfer and theinvention can correspond to the enhancement of the performance and thefunction of a mobile device.

In other words, data transfer between CHIP1 (FLASH) and CHIP3 (DRAM) bythe load instruction or the store instruction can be executed in thebackground, necessary data can be transferred to CHIP3 (DRAM) or CHIP1(FLASH) in advance by necessary time, and the invention can correspondto the enhancement of the performance and the function of a mobiledevice.

As described above, in the memory module according to the invention, theinformation processing device CHIP4 (MS) can activate itself promptlywith boot program data by following a method of providing the SRAMinterface and the SDRAM interface and automatically transferring theboot program data in CHIP1 (FLASH) to SRAM immediately after power isturned on. Further, as access to the memory module MM is possibleshortly when the information processing device CHIP4 (MS) is activatedby automatically transferring data in CHIP1 (FLASH) to CHIP3 (DRAM)while the information processing device CHIP4 (MS) activates itself, theperformance can be enhanced.

Data in FLASH can be read at the similar speed as that of DRAM bysecuring a region in which the data in CHIP1 (FLASH) can be copied inCHIP3 (DRAM) and transferring the data from CHIP1 (FLASH) to CHIP3(DRAM) in advance immediately after power is turned on or by a loadinstruction. As data is once written to DRAM and if necessary, can berewritten to FLASH by a store instruction when the data is written toFLASH, the writing speed of data is also similar to that of DRAM.

As inside the memory module MM, an error is detected and corrected inreading from FLASH and a defective address where writing is notcorrectly performed is replaced in writing, processing can be executedat high speed and the reliability can be kept.

As a program in CHIP1 (FLASH) can be changed via the buffer region ofSRAM and the contents of a program can be read and verified, flexiblecorrespondence in accordance with a request of a mobile device isenabled.

Further, as large-capacity DRAM is used, a large-capacity work regioncan be also secured in addition to a region in which data in FLASH canbe copied and the invention can correspond to the enhancement of thefunction of a mobile telephone.

FIG. 2 shows one example of a memory map by the memory management unitMU. In this embodiment, though the following are not particularlylimited, a representative memory map will be described using the memorymodule where a memory area of the non-volatile memory is 128 Mbits+4Mbits (4 Mbits are equivalent to a region for replacement), a memoryarea of DRAM is 256 Mbits, SRAM is 8 kbits and the control registersSREG and DREG are respectively 1 kbits for example below.

FIG. 2 shows the memory map in which the memory management unit MUconverts to an address in the control register DREG (1 kb), the workregion WK (128 Mbits) of DRAM, the copy region CP (128 Mbits) of DRAMand FLASH (128 Mbits) based upon an address input via the SDRAMinterface (SDRAM IF) and the SRAM interface (SRAM IF).

Though the following are not particularly limited, SRAM, the controlregister SREG, the bank 0 (BANK0) of DRAM, the bank 1 (BANK1), the bank2 (BANK 2), the bank 3 (BANK3) and the control register DREG are mappedin order from a lower part of address space of the memory map.

SRAM is divided into a boot region SBoot and a buffer region SBUF.

The bank 0 (BANK0) and the bank 1 (BANK1) of DRAM are mapped in the copyregion CP, and the bank 2 (BANK2) and the bank 3 (BANK3) are mapped inthe work region WK. The copy region CP is a region to which data inFLASH is transmitted and in which it is held. The work region WK is aregion utilized for a work memory. An initial automatic data transferregion IP is included in the copy region CP of the bank 1 (BANK1).

FLASH is divided into a main data region FM, an initial program regionFBoot and a replacement region FREP. An initial automatic data transferregion IP for implementing automatic transfer to DRAM when power isturned on is included in the main data region FM of FLASH.

A program and data are stored in the main data region FM of FLASH. Asfor FLASH, the reliability is deteriorated by repeating rewriting, thereoccur, though infrequently, that written data is rarely turned differentdata in reading and that no data is written in rewriting. Thereplacement region FREP is provided to reload data in the initialprogram region FBoot and the main data region FM respectively turneddefective as described above into a new region. The size of thereplacement region is not particularly limited, however, it is desirablethat the reliability which FLASH guarantees can be secured.

Data in the main data region FM and the replacement region FREP of FLASHare transferred to the copy region CP of DRAM according to a loadinstruction via the SDRAM interface (SDRAMIF).

Data transfer from FLASH to DRAM when power is turned on will bedescribed below.

In the initial program region FBoot of FLASH, designation data for anautomatic data transfer region showing a range of the initial automaticdata transfer region IP automatically transferred from FLASH to DRAMwhen power is turned on is stored.

After power is turned on, first, data in the initial program regionFBoot of FLASH is read, it is checked by the error correcting circuitECC whether the data has an error or not, and if the data has no error,the data is directly transferred to the boot region SBoot of SRAM. Incase the data has an error, data acquired by correcting the error istransferred to the boot region SBoot of SRAM.

Next, data shown in the designation data for the automatic data transferregion in the initial automatic data transfer region IP of FLASH istransferred to an initial automatic data transfer region CIP of DRAM.

Data transfer from FLASH to DRAM by a load instruction will be describedbelow.

A load instruction, a transfer initiation address and transfer data size(one page) are written to the control register DREG via the SDRAMinterface (SDRAM IF). Then, the control circuit CHIP2 (CTL_LOGIC) readsdata in the main data region FM of FLASH and transfers data for one pageto the copy region of DRAM according to the memory map set by the memorymanagement unit MU. When data is read from FLASH, it is checked by theerror correcting circuit ECC whether data in FLASH has an error or not,and if the data has no error, the data is directly transferred to thecopy region CP of DRAM. In case the data has an error, data acquired bycorrecting the error is transferred to the copy region CP of DRAM.

Data transfer from DRAM to FLASH by a store instruction will bedescribed below.

A store instruction, a transfer initiation address and transfer datasize (one page) are written to the control register DREG via the SDRAMinterface (SDRAM IF). Then, the control circuit CHIP2 (CTL_LOGIC) readsdata in the copy region of DRAM and transfers data for one page to themain data region of FLASH according to the memory map set by the memorymanagement unit MU.

When data is written to FLASH, the address replacement circuit REPchecks whether the writing succeeds or not and if the writing succeeds,the circuit finishes the processing. When the writing fails, the addressreplacement circuit selects an address in the replacement region FREP ofFLASH and writes data.

Next, reading data from DRAM will be described.

When an address in the bank 0 (BANK0) of DRAM in which data in the maindata region of FLASH is held and a read instruction are input via theSDRAM interface (SDRAM IF), the address in the bank 0 (BANK0) of DRAM isselected and the data can be read.

That is, data in FLASH can be read at the same speed as that of DRAM. Asfor the other banks (the bank 1, the bank 2, the bank 3), data can besimilarly read.

Next, writing data to DRAM will be described.

When an address in the bank 1 (BANK1) of DRAM and a write instructionare input via the SDRAM interface (SDRAM IF), the address in the bank 1(BANK1) of DRAM is selected and data can be written. As the data in thebank 1 (BANK1) of DRAM can be rewritten to FLASH by a store instructionif necessary, data in FLASH can be written at the same speed as that ofDRAM. As for the other banks (the bank 3, the bank 2, the bank 0), datacan be similarly written.

FIG. 3( a) and FIG. 3( b) show initial sequences when power is turned onof CHIP2 (CTL_LOGIC). First, FIG. 3( a) will be described.

For a period (PON) of T1, power is turned on and for a period (RST) ofT2, a reset is made. For the next period (BLD) of T3 in which the resetis released, data in the initial program region FBoot of FLASH istransferred to the boot region SBoot of SRAM. For a period (DINIT) ofT4, DRAM is initialized and for a period (ALD) of T5, data in theinitial automatic data transfer region IP of FLASH is transferred to theinitial automatic data transfer region CIP of DRAM. After transfer tothe initial automatic data transfer region CIP is started, the refreshcontrol circuit REF performs auto-refreshment. After transfer to theinitial automatic data transfer region CIP is finished, a data transfercompletion flag showing that the transfer is completed is written to thecontrol register DREG. For a period (IDLE) of T6 and later, DRAM isturned idle and access can be accepted via the SDRAM interface (SDRAMIF) of the information processing device CHIP4 (MS). When anauto-refresh instruction is input from the information processing deviceCHIP4 (MS) for a period (AREF) of T7, CHIP2 stops auto-refreshment bythe refresh control circuit REF and data-hold by refresh operationautomatically proceeds to refresh control from the informationprocessing device CHIP4 (MS).

As described above, access from the information processing device CHIP4(MS) is enabled without being conscious of refresh control from theinside of CHIP2 (CTL_LOGIC).

In FIG. 3( b), for a period of T6, the refresh control circuit REF turnsDRAM a self-refresh state according to a self-refresh instruction. Datatransferred to DRAM for a period (ALD) of 15 can be held with smallpower by turning DRAM the self-refresh state.

In the self-refresh state, data can be held with smaller power than thatin normal auto-refresh operation. When a self-refresh releaseinstruction from the information processing device CHIP4 (MS) forreleasing the self-refresh state is input for a period (SREX) T7, theself-refresh state is released, for a period (IDLE) of T8 and later,DRAM is turned idle, and access for reading or writing data can beaccepted. Data-hold by refresh operation automatically proceeds tocontrol from the information processing device CHIP4 (MS).

In case refresh control select data in the initial program region FBootof FLASH is at a high level, a sequence shown in FIG. 3A is executed andin case refresh control select data is at a low level, a sequence shownin FIG. 3B is executed. An input terminal PSQ only for selecting refreshcontrol may be also provided so that in case the input terminal PSQ isconnected to a power terminal, the initial sequence shown in FIG. 3A canbe selected and in case the input terminal PSQ is connected to an earthterminal, the initial sequence shown in FIG. 3B can be selected.

FIG. 4 is a flowchart showing one example of initialization applied togeneral purpose SDRAM for the period (DINT) of T4 shown in FIG. 3. Ininitializing DRAM, precharge is applied to all banks of DRAM (STEP1:ABP), next, auto-refreshment is applied (STEP2: AREF), and finally, amode register is set (STEP3: MRSET). Though the following are notparticularly limited, an example that burst length (BL) is set to 4 andCAS latency (CL) is set to 2 in setting the mode register (STEP3: MRSET)is shown.

FIG. 5 is a flowchart showing one example of initialization applied forthe period (DINT) of T4 to SDRAM which is acquired by adding an extendedmode register EMREG to conventional type general purpose SDRAM and inwhich a change of a data-hold region in self-refreshing, a change ofmaximum guarantee temperature and a change of the driveability of anoutput buffer are enabled.

In the initialization of this DRAM, precharge is applied to all banks ofDRAM (STEP1: ABP) and next, auto-refreshment is executed (STEP2: AREF).Amode register is set (STEP3: MRSET) and finally, an extended moderegister is set (STEP4: EMRSET). The following are not particularlylimited, however, there is shown an example that in setting the moderegister (STEP3: MRSET), burst length (BL) is set to 4, CAS latency (CL)is set to 2, in setting the extended mode register (STEP4: EMRSET), allbanks are set as the data-hold region of DRAM in self-refreshing(Ret=All banks), maximum guarantee temperature is set to 85° C.(Temp=85° C.), and the driveability of the output buffer is set to anormal value (Drv=Normal).

FIG. 6 is a flowchart showing one example of data transfer from FLASH toSRAM executed for the period (BLD) of T3 shown in FIG. 3 after power isturned on. After power is turned on, the control circuit CHIP2 readsdata in the initial program region FBoot from FLASH (STEP1). The controlcircuit checks whether the read data has an error or not (STEP2),corrects the error if the data has an error (STEP3), and directlytransfers the data to the boot region SBoot of SRAM in case the data hasno error (STEP4).

FIG. 7 is a flowchart showing one example of data transfer from theinitial automatic data transfer region IP of FLASH to the initialautomatic data transfer region CIP of DRAM executed for the period (ALD)of T5 shown in FIG. 3 after power is turned on. After power is turnedon, the control circuit CHIP2 reads data from FLASH (STEP1). The controlcircuit checks whether the read data has an error or not (STEP2),corrects the error if the data has an error (STEP3), and directlytransfers the data to the data buffer BUF in case the data has no error(STEP4).

When the data written to the data buffer BUF is written to DRAM, it ischecked whether a refresh request is made to DRAM or not (STEP5), if therefresh request is made, refresh operation is executed (STEP6), andafterward, the data is written to DRAM (STEP7). In case no refreshrequest is made, the data is written to DRAM promptly (STEP7). It ischecked whether all data in the data buffer BUF are written to DRAM ornot (STEP8) and if not all of data are written, STEP5 to STEP8 arerepeated. Next, it is checked whether data in the initial automatic datatransfer region IP of FLASH are all written to DRAMor not (STEP9). Incase not all of data are written, STEP1 to STEP9 are repeated. If datain the initial automatic data transfer region IP of FLASH are allwritten to DRAM, a value showing that the data transfer is completed iswritten to the control register DREG (STEP10).

The refresh control circuit REF issues an auto-refresh instruction toDRAM after the initialization of DRAM for the period (ALD) of T5 shownin FIG. 3 and holds data in DRAM until an auto-refresh instruction or aself-refresh instruction is input from the information processing deviceCHIP4 (MS).

FIG. 8 is a flowchart showing data transfer from FLASH to DRAM executedaccording to a load instruction.

When a load instruction and an address are input to CHIP2 (CTL_LOGIC)from the information processing device CHIP4 (MS) (STEP1), datacorresponding to the input address is read from FLASH (STEP2). It ischecked whether the read data has an error or not (STEP3), if the datahas an error, the error is corrected (STEP4), and data after correctionis written to the data buffer BUF (STEP5). In case the data has noerror, the data is directly written to the data buffer BUF (STEP5).

Before the data written to the data buffer BUF is written to DRAM, it ischecked whether a read instruction, a write instruction or a refreshinstruction is issued from the information processing device CHIP4 (MS)to DRAM or not (STEP6), if such an instruction is issued, theinstruction is executed (STEP7), and afterward, writing data to DRAM isstarted (STEP8). In case no instruction is issued, writing the data toDRAM is started promptly (STEP8).

Next, it is checked whether data are all written from the data bufferBUF to DRAM or not (STEP9). In case not all of data are written, thatis, during writing, it is checked whether a read instruction, a writeinstruction or a refresh instruction is issued from the informationprocessing device CHIP4 (MS) to DRAM or not (STEP10), if such aninstruction is issued, write operation from the data buffer BUF to DRAMis temporarily halted (STEP11), and the instruction is executed(STEP12). It is checked whether the instruction is finished or not(STEP13) and if the instruction is not finished, STEP11 and STEP13 arerepeated. In case the instruction is finished, write operation from thedata buffer BUF to DRAM is restarted (STEP8). When data are all writtenfrom the data buffer BUF to DRAM, a value showing that the data transferis finished is written to the control register DREG (STEP14).

FIG. 9 is a flowchart showing data transfer from DRAM to FLASH executedby a store instruction.

When a store instruction and an address are input from the informationprocessing device CHIP4 (MS), CHIP2 takes a procedure for reading datafrom DRAM according to the store instruction inside (STEP1). Beforereading data from DRAM according to the store instruction is started, itis checked whether a read instruction, a write instruction or a refreshinstruction is issued from the information processing device CHIP4 (MS)or not (STEP2). In case no instruction is issued, reading data from DRAMaccording to the store instruction is started (STEP5).

In case such an instruction is issued, the execution of the storeinstruction is temporarily halted (STEP3) and it is checked whether thecurrently executed instruction is completed or not (STEP4). In case theexecution of the instruction is not completed, the execution of thestore instruction is halted (STEP3). If the execution of the instructionis completed, reading data from DRAM according to the store instructionis started and the data read from DRAM is written to the data buffer BUF(STEP5).

It is checked whether writing the data read from DRAM according to thestore instruction to the data buffer BUF is finished or not (STEP6).When writing is not finished and writing is continued, it is checkedwhether a read instruction, a write instruction or a refresh instructionis issued from the information processing device CHIP4 (MS) or not(STEP7), in case such an instruction is issued, the read operation ofdata fromDRAMis temporarilyhalted (STEP8), and the instruction isexecuted (STEP9).

It is checked whether the instruction is finished or not (STEP10), ifthe instruction is not finished, STEP8 and STEP10 are repeated, in casethe instruction is finished, read operation from DRAM is restarted, andread data is written to the data buffer BUF (STEP5).

When the data in the data buffer BUF is written to FLASH (STEP11), thedata read from DRAM and transferred to the data buffer BUF is written toFLASH.

It is checked whether the writing to FLASH succeeds or not (STEP12), incase the writing fails, another address for replacement is selected(STEP13), and writing to FLASH (STEP11) is executed again. In case thewriting succeeds, it is checked whether data transfer according to thestore instruction is completed or not (STEP11), if the data transfer isnot completed, writing to FLASH (STEP11) is continued, and in case thedata transfer is completed, a value showing that the data transfer isfinished is written to the control register DREG (STEP15).

FIG. 10 is a flowchart showing data transfer from FLASH to SRAM executedaccording to a load instruction (SLoad).

When a load instruction and an address are input to CHIP2 from theinformation processing device CHIP4 (MS) (STEP1), data corresponding tothe input address is read from FLASH (STEP2). It is checked whether theread data has an error or not (STEP3), if the data has an error, theerror is corrected (STEP4), and data after correction is written to SRAM(STEP5). In case the data has no error, the data is directly written toSRAM (STEP5).

It is checked whether writing to SRAM according to the load instructionis finished or not (STEP6), if the writing is not finished, STEP5 andSTEP6 are repeated. In case the writing is completed, a value showingthat data transfer is finished is written to the control register SREG(STEP7).

FIG. 11 is a flowchart showing data transfer from SRAM to FLASH executedaccording to a store instruction.

When a store instruction and an address are input to CHIP2 from theinformation processing device CHIP4 (MS) (STEP1), data is read from SRAM(STEP2), and is written to FLASH (STEP3). It is checked whether thewriting to FLASH succeeds or not (STEP4), in case the writing fails,another address for replacement is selected (STEP5), and the data iswritten to FLASH again (STEP4). In case the writing succeeds, it ischecked whether data transfer according to the store instruction isfinished or not (STEP6) and if the data transfer is not completed, STEP2to STEP6 are repeated. If the data transfer is finished, a value showingthat the data transfer is finished is written to the control registerSREG (STEP7).

FIG. 12 is a block diagram showing one example of a NAND type flashmemory equipped with a NAND interface (NAND IF) and used for CHIP1(FLASH) shown in FIG. 1 and configuring this memory module MM.

The NAND type flash memory is configured by an operating logiccontroller L-CONT, a control circuit CTL, an input/output controlcircuit I/O-CONT, a status register STREG, an address register ADREG, acontrol register COMREG, a ready/busy circuit R/B, a high-voltagegenerator VL-GEN, a row address buffer ROW-BUF, a row address decoderROW-DEC, a column buffer COL-BUF, a column decoder COL-DEC, a dataregister DATA-REG, a sense amplifier SENSE-AMP and a memory array MA.

The operation of CHIP1 (FLASH) is similar to that of a NAND type flashmemory used generally heretofore.

FIG. 13 shows data read operation from the NAND type flash memoryconfiguring CHIP1. When a chip enable signal F-/CE is turned at a lowlevel, a command latch enable signal F-CLE is turned at a high level anda write enable signal F-/WE is activated, a read instruction code Rcodeis input in the form of input/output signals F-I00 to F-I015. Afterward,an address latch enable signal F-ALE is turned at a high level and apage address is input in the form of the input/output signals F-I00 toF-I07 at second, third and fourth leading edges of the write enablesignal F-/WE.

Data for one page corresponding to the input page address is transferredfrom a memory array MA to a data register DATA-REG. While the data istransferred from the memory array MA to the data register DATA-REG, theflash memory is turned busy and the ready/busy circuit R/B turns aready/busy signal F-R/B at a low level. When data transfer is finished,data in the data register DATA-REG is read in order by 8 bits insynchronization with a trailing edge of the read enable signal F-/RE andis output in the form of the input/output signals F-I00 to F-I07.

FIG. 14 shows an example of the configuration in case an AND type flashmemory equipped with an AND interface (AND IF) is used for CHIP1 (FLASH)of this memory module MM. In case the AND type flash memory equippedwith the AND interface (AND IF) is used, this memory system can be alsoimplemented.

FIG. 15 is a block diagram showing an AND flash memory used for CHIP1 inthis memory module.

CHIP1 (FLASH) which is the AND type flash memory is configuredby acontrol signal buffer C-BUF, a command controller C-CTL, a multiplexerMUX, a data input buffer DI-BUF, an input data controller IDC, a sectoraddress buffer SA-BUF, an X decoder X-DEC, a memory array MA (AND TYPE),a Y address counter Y-CTF, a Y decoder Y-DEC, a sense amplifierY-GATE/SENS AMP, a data register Data Register and a data output bufferDO-BUF. The operation of CHIP1 is similar to that of an AND type flashmemory used generally heretofore. The memory module in this embodimentcan be configured by CHIP1 (FLASH).

FIG. 16 shows data read operation from the AND type flash memoryconfiguring CHIP1.

When a chip enable signal F-/CE is turned at a low level, a command dataenable signal F-CDE is turned at a low level and a write enable signalF-/WE is activated, a read instruction code Rcode is input in the formof input/output signals F-I00 to F-I07. A sector address is input in theform of the input/output signals F-I00 to F-I07 at second and thirdleading edges of the write enable signal F-/WE.

Data for one page corresponding to the input sector address istransferred from the memory array MA to the data register Data Register.While the data is transferred from the memory array MA (AND TYPE) to thedata register Data Register, FLASH is turned busy and F-R/B turns aready/busy signal at a low level. When the data transfer is finished,data in the data register DATA-REG is read in order by 8 bits insynchronization with a leading edge of a serial clock signal F-SC and isoutput in the form of the input/output signals F-I00 to F-I07.

As described above, in the memory module according to the invention, theinformation processing device CHIP4 (MS) can activate itself promptlywith boot program data by following a method of providing the SRAMinterface and the SDRAM interface and automatically transferring theboot program data in CHIP1 (FLASH) to SRAM immediately after power isturned on. Further, as prompt access to the memory module MM is enabledwhen the information processing device CHIP4 (MS) is activated byautomatically transferring data in CHIP1 (FLASH) to CHIP3 (DRAM) whilethe information processing device CHIP4 (MS) activates itself, theperformance can be enhanced.

As data transfer between CHIP1 (FLASH) and CHIP3 (DRAM) by a loadinstruction and a store instruction can be executed in the background,necessary data can be transferred to CHIP3 (DRAM) or to CHIP1 (FLASH) inadvance by necessary time without being conscious of access from theoutside of the memory module and the invention can correspond to theenhancement of the performance and the function of a mobile device.

Data in FLASH can be read at the similar speed to that of DRAM bysecuring a region in which the data in CHIP1 (FLASH) can be copied inCHIP3 (DRAM) and transferring data from CHIP1 (FLASH) to CHIP3 (DRAM) inadvance immediately after power is turned on or by a load instruction.As data is once written to DRAM when it is written to FLASH and can berewritten to FLASH by a store instruction if necessary, the write speedof data is also similar to that in DRAM.

As inside the memory module MM, the detection and the correction of anerror are performed in reading from FLASH and a defective address towhich data is not correctly written is replaced in writing, theprocessing is enabled at high speed and the reliability can be kept.

As a program in CHIP1 (FLASH) can be changed via the buffer region ofSRAM and the contents of a program can be read and verified via thebuffer region of SRAM, the invention can flexibly correspond to arequest of a mobile device.

Further, as large-capacity DRAM is used, the large-capacity work regioncan be also secured in addition to the region in which data in FLASH canbe copied and the invention can correspond to the enhancement of thefunction of a mobile device.

Second Embodiment

FIG. 17 shows a second embodiment to which the invention is applied.Detailedly, FIG. 17 shows the embodiment of a memory system configuredby a memory module MM1 and an information processing device CHIP4 (MS).Each will be described below.

The memory module MM1 is configured by CHIP1 (FLASH), CHIP2 (CTL_LOGIC1)and CHIP3 (DRAM1).

CHIP1 (FLASH) is a non-volatile memory and will be described as alarge-capacity flash memory equipped with a NAND interface (NAND IF)though the above-mentioned is not particularly limited below. CHIP1(FLASH) has large memory size of approximately 128 Mbits, read time(time since a request for reading is made until data is output) isapproximately 25 to 100 μs and is relatively slow.

CHIP3 (DRAM1) is DRAM equipped with an interface for data transferto/from CHIP2 (CTL_LOGIC1) and an interface for data transfer to/fromthe information processing device CHIP4 (MS).

The interface for data transfer to/from the information processingdevice CHIP4 (MS) has two types of an asynchronous DRAM interface and asynchronous DRAM interface and both interfaces can be used for thememory module MM1. In this embodiment, an SDRAM interface (SDRAM IF)which is the synchronous DRAM interface and is a typical synchronousDRAM interface will be described as an example.

The interface used for data transfer between CHIP3 (DRAM1) and CHIP2(CTL_LOGIC1) is a flash memory interface, has two types of a so-calledAND interface (AND IF) and a so-called NAND interface (NAND IF), and inthis embodiment, both can be used. In this embodiment, the interface fordata transfer to/from CHIP3 (DRAM1) and CHIP2 (CTL_LOGIC1) will bedescribed as the NAND interface.

Next, the configuration of CHIP3 (DRAM1) will be described. CHIP3(DRAM1) is configured by memory banks (B0, B1, B2, B3) for holding dataand a control circuit DCTL1 for controlling reading and writing datafrom/to the memory banks. The control circuit DCTL1 is configured by acommand decoder CDEC, an access arbiter ARB, a memory management unitDMU, an initialize circuit INT, a refresh control circuit REF, a databuffer BUF, a control register DREG, a mode register MR, an extendedmode register EMR and a FLASH interface circuit FIF.

CHIP1 (FLASH) is divided into an initial program region and a main dataregion though the above-mentioned is not particularly limited, CHIP3(DRAM1) is divided into a work region and a copy region through theabove-mentioned is not particularly limited, and is managed by thememory management unit DMU so that the work region is used for a workmemory when a program is executed and the copy region is used for amemory for copying data from FLASH. The memory banks B0 and B1 of CHIP3(DRAM1) can be also allocated to the copy region and the memory banks B2and B3 can be also allocated to the work region.

CHIP2 (CTL_LOGIC1) is configured by SRAM, a control register SREG, aflash control circuit FCON, an error detecting and correcting circuitECC, an address replacement circuit REP and a memory management unit SMUand controls data transfer between CHIP1 (FLASH) and CHIP3 (DRAM1).

SRAM is divided into a boot program region and a buffer region thoughthe above-mentioned is not particularly limited and is managed by thememory management unit SMU so that the boot program region is used forstoring boot program data for activating the information processingdevice CHIP4 (MS) and the buffer region is used for a buffer memory fordata transfer between CHIP1 (FLASH) and SRAM.

Data transfer between CHIP1 (FLASH) and CHIP2 (CTL_LOGIC1) is performedvia the NAND interface (NAND IF) and data transfer between CHIP2(CTL_LOGIC1) and CHIP3 (DRAM1) is performed via the SDRAM interface(SDRAM IF). Data transfer to/from the information processing deviceCHIP4 (MS) is performed via an SRAM interface (SRAM IF).

The information processing device CHIP4 (MS) is configured by a centralprocessing unit (CPU), an SRAM controller SRC and a DRAM controller SDC.The SRAM controller accesses SRAM of CHIP2 (CTL_LOGIC1) via the SRAMinterface (SRAM IF) to read or write data. The DRAM controller directlyaccesses CHIP3 (DRAM1) via the SDRAM interface (SDRAM IF) to read orwrite data.

As described above, in this embodiment, as the information processingdevice CHIP4 (MS) and CHIP3 (DRAM1) can be directly connected via theSDRAM interface (SDRAM IF) without requiring a chip between them becauseCHIP3 (DRAM1) is provided with the plural interfaces of the SDRAMinterface (SDRAM IF) and the NAND interface (NAND IF), data can be readat higher speed. Further, CHIP3 (DRAM1) and CHIP2 (CTL_LOGIC1) areconnected via the NAND interface (NAND IF), the number of connectedwires is reduced, and the cost can be reduced.

Next, the operation of this embodiment will be described.

When power is turned on, CHIP1 (FLASH), CHIP2 (CTL_LOGIC1) and CHIP3(DRAM1) set themselves to an initial condition.

Next, the flash control circuit FCON reads data in an initial programregion FBoot of CHIP1 (FLASH) and instructs the error detecting andcorrecting circuit ECC to check whether the data has an error or not. Ifthe data has no error, the data is directly transferred to a bootprogram region SBoot of SRAM, in case the data has an error, the erroris corrected, and is transferred to the boot program region of SRAM.

The information processing device CHIP4 (MS) reads boot program datastored in the boot program region of SRAM to activate itself.

Besides, the initialize circuit INT sets the mode register MR and theextended mode register EMR to a desired value as an initializationsequence of CHIP3 (DRAM1).

When the flash control circuit FCON informs CHIP3 (DRAM1) that transferto the boot program region of SRAM is finished via the flash interfacecircuit FIF while the information processing device CHIP4 (MS) activatesitself, CHIP3 (DRAM1) instructs the flash control circuit FCON to enabledata transfer from CHIP1 (FLASH) to CHIP3 (DRAM1) via the FLASHinterface circuit FIF. Afterward, the flash control circuit FCONsequentially reads data in the main data region of CHIP1 (FLASH) andinstructs the error detecting and correcting circuit ECC to checkwhether the data has an error or not. If the data has no error, the datais directly transferred to the data buffer BUF, in case the data has anerror, the error is corrected, and data after correction is transferredto the data buffer BUF via the FLASH interface circuit FIF. The commanddecoder CDEC sequentially transfers the data held in the data buffer BUFto the memory bank 0 (B0) allocated to the copy region. When datatransfer is started, the refresh control circuit executes refreshoperation to hold the data transferred to the memory bank 0 (B0).

When a load instruction is written to the control register SREG of CHIP2(CTL_LOGIC1) from the information processing device CHIP4 (MS) via theSRAM interface (SRAM IF), data in the main data region of CHIP1 (FLASH)is transferred to the buffer region of SRAM. When a store instruction iswritten to the control register SREG, data in the buffer region of SRAMis transferred to the main data region of CHIP1 (FLASH).

When a load instruction is written to the control register DREG of CHIP3(DRAM1) from the information processing device CHIP4 (MS) via the SDRAMinterface (SDRAM IF), data in the main data region of CHIP1 (FLASH) istransferred to the copy region of CHIP3 (DRAM1) via CHIP2. When a storeinstruction is written to the control register DREG, data in the copyregion of CHIP3 (DRAM1) is written to the main data region of CHIP1(FLASH) via CHIP2 (CTL_LOGIC1).

When an instruction to read CHIP1 (FLASH) data held in the memory bank 0(B0) of CHIP3 (DRAM1) and an address are input from the informationprocessing device CHIP4 (MS) via the SDRAM interface (SDRAM IF), theaccess arbiter ARB always precedes the read instruction from theinformation processing device CHIP4 (MS) and stops data transfer if thedata transfer between CHIP1 (FLASH) and CHIP3 (DRAM1) is performed by aload instruction or a store instruction. Afterward, the command decoderCDEC decodes the read instruction, reads data from the memory bank 0(B0), and outputs it via the SDRAM interface.

In case the AND interface (AND IF) is used for data transfer to/fromCHIP1 (FLASH) of this memory module MM1 and the AND interface (AND IF)is used for data transfer between CHIP3 (DRAM1) and CHIP2 (CTL_LOGIC1),it is needless to say that this memory system can be also implemented.

As described above, prompt access to the memory banks (B0, B1, B2, B3)is enabled by building the access arbiter ARB and the command decoderCDEC in CHIP3 (DRAM1) and CHIP1 (FLASH) data can be read at high speed.Further, as CHIP3 (DRAM1) is provided with the SDRAM interface (SDRAMIF) and the NAND interface (NAND IF), the SDRAM interface (SDRAM IF) canbe directly connected to the information processing device CHIP4 (MS)and as data transfer is enabled between the information processingdevice CHIP4 (MS) and CHIP3 (DRAM1) without requiring a chip, data canbe read at high speed.

Third Embodiment

FIG. 18 shows a third embodiment to which the invention is applied. FIG.18 shows an embodiment of a memory system configured by a memory moduleMM2 and an information processing device CHIP4 (MS). Each will bedescribed below.

The memory module MM2 is configured by CHIP1 (FLASH2), CHIP2(CTL_LOGIC2) and CHIP3 (DRAM2).

CHIP1 (FLASH2) is a non-volatile memory and is a large-capacity flashmemory equipped with a NAND interface (NAND IF) though theabove-mentioned is not particularly limited.

CHIP1 (FLASH2) is configured by a non-volatile memory array MA forholding data, a control circuit FCTL for controlling reading and writingdata from/to the non-volatile memory array, an error detecting andcorrecting circuit ECC and an address replacement circuit REP.

As for the configuration of the memory array MA, there are NANDconfiguration and AND configuration and both can be used.

CHIP3 (DRAM2) is DRAM provided with an interface for data transferto/from CHIP1 (FLASH2) and an interface for data transfer to/from theinformation processing device CHIP4 (MS).

The interface for data transfer to/from the information processingdevice (MS) has two types of an asynchronous DRAM interface and asynchronous DRAM interface and in the memory module MM2, both interfacescan be used. This embodiment will be described using an SDRAM interface(SDRAM IF) which is the synchronous DRAM interface and is typically usedas an example below.

The interface for data transfer between CHIP3 (DRAM2) and CHIP1 (FLASH2)is a flash memory interface, the interface for a flash memory has twotypes of an AND interface (AND IF) and a NAND interface (NAND IF), andin this embodiment, both can be used. In this embodiment, the interfacefor data transfer between CHIP3 (DRAM) and CHIP1 (FLASH2) will bedescribed as the NAND interface.

Next, the configuration of CHIP3 (DRAM2) will be described. CHIP3(DRAM2) is configured by memory banks (B0, B1, B2, B3) for holding dataand a control circuit DCTL2 for controlling reading and writing datafrom/to the memory bank. The control circuit DCTL2 is configured by acommand decoder CDEC, an access arbiter ARB, a memory management unitDMU, an initialize circuit INT, a refresh control circuit REF, a databuffer BUF, a control register DREG, a mode register MR, an extendedmode register EMR and a flash control circuit DFCON.

CHIP1 (FLASH2) is divided into an initial program region and a main dataregion though the above-mentioned is not particularly limited, CHIP3(DRAM2) is divided into a work region and a copy region though theabove-mentioned is not particularly limited, and is managed by thememory management unit DMU so that the work region is used for a workmemory when a program is executed and the copy region is used for amemory for copying data from FLASH. The memory banks B0 and B1 of CHIP3(DRAM2) can be also allocated to the copy region and the memory banks B2and B3 can be also allocated to the work region.

CHIP2 (CTL_LOGIC2) is configured by SRAM, a control register SREG, aflash control circuit SFCON and a memory management unit SMU andcontrols data transfer to/from CHIP1 (FLASH2).

SRAM is divided into a boot program region and a buffer region thoughthe above-mentioned is not particularly limited and is managed by thememory management unit SMU so that the boot program region is used forstoring boot program data for activating the information processingdevice CHIP4 (MS) and the buffer region is used for a buffer memory forenabling data transfer between CHIP1 (FLASH2) and SRAM.

Data transfer between CHIP1 (FLASH2) and CHIP2 (CTL_LOGIC2) is performedvia the NAND interface (NAND IF) and data transfer to/from theinformation processing device CHIP4 (MS) is performed via the SRAMinterface (SRAM IF).

The information processing device CHIP4 (MS) is configured by a centralprocessing unit CPU, an SRAM controller SRC and a DRAM controller SDC.The SRAM controller SRC accesses SRAM of CHIP2 (CTL_LOGIC2) via the SRAMinterface (SRAM IF) to read or write data. The DRAM controller SDCdirectly accesses CHIP3 (DRAM2) via the SDRAM interface (SDRAM IF) toread or write data.

As described above, in this embodiment, as CHIP1 (FLASH2) is providedwith the error detecting and correcting circuit ECC and the addressreplacement circuit REP inside, the detection and the correction of anerror in reading data can be performed at high speed and as thereplacement of an address in writing data can be also performed at highspeed, data transfer can be sped up.

Further, as CHIP3 (DRAM2) is provided with the SDRAM interface (SDRAMIF) and the NAND interface (NAND IF), the NAND interface (NAND IF) canbe directly connected to CHIP1 (FLASH2) and the SDRAM interface (SDRAMIF) can be directly connected to the information processing device CHIP4(MS), data can be read at higher speed.

Next, the operation of this embodiment will be described.

When power is turned on, CHIP1 (FLASH2), CHIP2 (CTL_LOGIC2) and CHIP3(DRAM2) set themselves to an initial condition.

Next, the flash control circuit SFCON reads data in the initial programregion of CHIP1 (FLASH2) and transfers it to the boot program region ofSRAM.

In CHIP1 (FLASH2), the error detection and the error correction of dataare performed at high speed by the built-in error detecting andcorrecting circuit ECC in reading the data.

The information processing device CHIP4 (MS) reads boot program datastored in the boot program region of SRAM to activate itself.

The initialize circuit INT sets the mode register MR and the extendedmode register EMR to a desired value as an initialization sequence ofCHIP3 (DRAM2).

While the information processing device CHIP4 (MS) activates itself, theflash control circuit SFCON informs CHIP3 (DRAM2) that data transfer tothe boot program region of SRAM is finished in the form of a datatransfer termination signal TC. Afterward, the flash control circuitDFCON of CHIP3 (DRAM2) sequentially reads data in the main data regionof CHIP1 (FLASH2) and transfers it to the data buffer BUF. The commanddecoder CDEC sequentially transfers the data held in the data buffer BUFto the memory bank 0 (B0) allocated to the copy region. When datatransfer is started, the refresh control circuit performs refreshoperation to hold the data transferred to the memory bank.

When a load instruction is written to the control register SREG of CHIP2(CTL_LOGIC2) from the information processing device CHIP4 (MS) via theSRAM interface (SRAM IF), data in the main data region of CHIP1 (FLASH2)is transferred to the buffer region of SRAM. When a store instruction iswritten to the control register SREG, data in the buffer region of SRAMis transferred to the main data region of CHIP1 (FLASH2). When data iswritten to CHIP1 (FLASH2), it is checked at high speed by the built-inaddress replacement circuit REP whether the writing succeeds or not, ifthe writing succeeds, the writing is finished, when the writing fails,an address in an address replacement region FREP of FLASH is selected,and the data is written to it.

When a load instruction is written to the control register DREG of CHIP3(DRAM) from the information processing device CHIP4 (MS) via the SDRAMinterface (SDRAM IF), data in the main data region of CHIP1 (FLASH2) isdirectly transferred to the copy region of CHIP3 (DRAM2). When a storeinstruction is written to the control register DREG, data in the copyregion of CHIP3 (DRAM2) is directly written to the main data region ofCHIP1 (FLASH2).

When an instruction to read CHIP1 (FLASH2) data held in the memory bank0 (B0) of CHIP3 (DRAM2) and an address are input from the informationprocessing device CHIP4 (MS) via the SDRAM interface (SDRAM IF), theaccess arbiter ARB always precedes the read instruction from theinformation processing device CHIP4 (MS) and stops data transfer if thedata transfer between CHIP1 (FLASH2) and CHIP3 (DRAM2) is performed by aload instruction or a store instruction. Afterward, the command decoderCDEC decodes the read instruction, reads data from the memory bank 0(B0), and outputs it via the SDRAM interface.

It is needless to say that in case the AND interface (AND) is used fordata transfer between CHIP1 (FLASH2) and CHIP3 (DRAM2) in this memorymodule MM2, this memory module can be also implemented.

As described above, in this embodiment, as the error detecting andcorrecting circuit ECC and the address replacement circuit REP are builtin CHIP1 (FLASH2), error detection and error correction in reading datacan be performed at high speed and as the replacement of an address inwriting data can be also made at high speed, data transfer can be spedup.

Further, as CHIP3 (DRAM2) is provided with the SDRAM interface (SDRAMIF) and the NAND interface (NAND IF), the NAND interface (NAND IF) canbe directly connected to CHIP1 (FLASH2) and the SDRAM interface (SDRAMIF) can be directly connected to the information processing device CHIP4(MS), data can be read at higher speed.

FIG. 19 is a block diagram showing one example of the flash memory usedfor CHIP1 (FLASH2) shown in FIG. 18 configuring this memory module MM2.

The flash memory is configured by a control signal buffer CSB, aread/program/erase control circuit RPEC, a sector address buffer SABUF,an X decoder X-DEC, a multiplexing circuit MLP, a Y address counter YAC,a data input buffer DIBUF, an input data control circuit IDC, a dataoutput buffer DOBUF, a Y decoder Y-DEC, a Y gate circuit Y-GT, a dataregister DTREG and a memory array MA.

FIG. 20 shows data read operation from the flash memory of CHIP1(FLASH2). When a chip enable signal F-/CE is turned at a low level, acommand latch enable signal F-CLE is turned at a high level and a writeenable signal F-/WE is activated, an instruction code Rcode of a readinstruction is input in the form of input/output signals F-I01 to F-I08.Afterward, an address latch enable signal F-ALE is turned at a highlevel and addresses (CA1, CA2, SA1, SA2) are input in the form of theinput/output signals F-I01 to F-I08 at a leading edge of the writeenable signal F-/WE. A start address is specified by CA1 and CA2 and asector address is specified by SA1 and SA2.

Data for one sector corresponding to the input sector address istransferred from the memory array MA to the data register DTREG. Whilethe data is transferred from the memory array MA to the data registerDTREG, the flash memory is turned busy and a ready/busy circuit R/Bturns a ready/busy signal F-R/B at a low level. When the data transferto the data register DTREG is finished, data in the data register DTREGis read in order from the input start address by 16 bits insynchronization with a read enable signal F-/RE and is output in theform of input/output signals F-I01 to F-I016.

Fourth Embodiment

FIG. 21 shows a fourth embodiment to which the invention is applied.FIG. 21 shows an embodiment of an information processing systemconfigured by a memory module MM3 and an information processing deviceCHIP4 (MS). Each will be described below.

The memory module MM3 is configured by CHIP1 (FLASH3) and CHIP3 (DRAM3).CHIP1 (FLASH3) is a non-volatile memory and is a large-capacity flashmemory equipped with a NAND interface (NAND IF) though theabove-mentioned is not particularly limited.

CHIP1 (FLASH3) is configured by a non-volatile memory array MA forholding data, a transfer control circuit FCTL3 for controlling datatransfer from the non-volatile memory array MA to SRAM, an errordetecting and correcting circuit ECC, an address replacement circuitREP, SRAM, a control register SREG and a memory management unit SMU.

SRAM is divided into a boot program region and a buffer region thoughthe above-mentioned is not particularly limited and is managed by thememory management unit SMU so that the boot program region is used forstoring boot program data for activating the information processingdevice CHIP4 (MS) and the buffer region is used for a buffer memory fordata transfer between the non-volatile memory array MA of CHIP1 (FLASH3)and SRAM.

The configuration of the memory array MA mainly has two types of NANDconfiguration and AND configuration and both can be used.

CHIP3 (DRAM3) is DRAM equipped with an interface for data transferto/from CHIP1 (FLASH3) and an interface for data transfer to/from theinformation processing device CHIP4 (MS).

The interface for data transfer to/from the information processingdevice CHIP4 (MS) has two types of an asynchronous DRAM interface and asynchronous DRAM interface and both can be used in the memory moduleMM2. This embodiment will be described using an SDRAM interface (SDRAMIF) which is the synchronous DRAM interface typically used for anexample below.

The interface for data transfer between CHIP3 (DRAM3) and CHIP1 (FLASH3)is a flash memory interface, the flash memory interface has two types ofan AND interface (AND IF) and a NAND interface (NAND IF), and in thisembodiment, both can be used. In this embodiment, the interface for datatransfer between CHIP3 (DRAM3) and CHIP1 (FLASH3) will be described asthe NAND interface below.

Next, the configuration of CHIP3 (DRAM3) will be described. CHIP3(DRAM3) is configured by memory banks (B0, B1, B2, B3) for holding dataand a control circuit DCTL3 for controlling reading and writing datafrom/to the memory bank. The control circuit DCTL3 is configured by acommand decoder CDEC, an access arbiter ARB, a memory management unitDMU, an initialize circuit INT, a refresh control circuit REF, a databuffer BUF, a control register DREG, a mode register MR, an extendedmode register EMR and a flash control circuit DFCON.

By the memory management unit DMU, CHIP1 (FLASH3) is divided into aninitial program region and a main data region though the above-mentionedis not particularly limited, CHIP3 (DRAM3) is divided into a work regionand a copy region though the above-mentioned is not particularlylimited, and is managed so that the work region is used for a workmemory when a program is executed and the copy region is used for amemory for copying data from CHIP1 (FLASH3). The memory banks B0 and B1of CHIP3 (DRAM3) can be also allocated to the copy region and the memorybanks B2 and B3 can be also allocated to the work region.

The information processing device CHIP4 (MS) is configured by a centralprocessing unit CPU, an SRAM controller SRC and a DRAM controller SDC.The SRAM controller accesses SRAM of CHIP1 (FLASH3) via an SRAMinterface (SRAM IF) to read or write data. The DRAM controller directlyaccesses CHIP3 (DRAM3) via the SDRAM interface (SDRAM IF) to read orwrite data.

As described above, in this embodiment, as SRAM, the error detecting andcorrecting circuit ECC and the address replacement circuit REP are builtin CHIP1 (FLASH3), data transfer between the non-volatile memory arrayand SRAM can be performed at high speed.

As CHIP3 (DRAM3) is provided with the SDRAM interface (SDRAM IF) and theNAND interface (NAND IF), the NAND interface (NAND IF) can be directlyconnected to CHIP1 (FLASH3) and the SDRAM interface (SDRAM IF) can bedirectly connected to the information processing device CHIP4 (MS), datacan be read at higher speed.

Further, as the number of chips for implementing this memory system canbe reduced, the power and the cost can be reduced.

Next, the operation of this embodiment will be described.

When power is turned on, CHIP1 (FLASH3) and CHIP3 (DRAM3) set themselvesto an initial condition.

Next, the transfer control circuit FCTL3 reads data in the initialprogram region of the non-volatile memory array MA and transfers it tothe boot program region of SRAM.

When the data is read from the non-volatile memory array MA of CHIP1(FLASH3), error detection and error correction are performed at highspeed by the built-in error detecting and correcting circuit ECC.

The information processing device CHIP4 (MS) reads boot program datastored in the boot program region of SRAM and activates itself.

The initialize circuit INT sets the mode register MR and the extendedmode register EMR to a desired value as a sequence for initializingCHIP3 (DRAM3).

While the information processing device CHIP4 (MS) activates itself, thetransfer control circuit FCTL3 informs that data transfer to the bootprogram region of SRAM is finished in the form of a data transfertermination signal TC. Afterward, the flash control circuit DFCON ofCHIP3 (DRAM3) sequentially reads data in the main data region of thenon-volatile memory array MA via the transfer control circuit FCTL3 andtransfers the data to the data buffer BUF. The command decoder CDECsequentially transfers the data held in the data buffer BUF to thememory bank 0 (B0) allocated to the copy region. When data transfer isstarted, the refresh control circuit executes refresh operation to holdthe data transferred to the memory bank.

When a load instruction is written from the information processingdevice CHIP4 (MS) to the control register SREG of CHIP1 (FLASH3) via theSRAM interface (SRAM IF), data in the main data region held in thenon-volatile memory array MA is transferred to the buffer region ofSRAM. When a store instruction is written to the control register SREG,data in the buffer region of SRAM is transferred to the main data regionof the non-volatile memory array MA.

When data is written to the non-volatile memory array MA, it is checkedat high speed by the built-in address replacement circuit REP whetherthe writing succeeds or not, if the writing succeeds, it is finished,when the writing fails, an address in an address replacement region FREPof CHIP1 (FLASH3) is selected, and the data is written there.

When a load instruction is written from the information processingdevice CHIP4 (MS) to the control register DREG of CHIP3 (DRAM3) via theSDRAM interface (SDRAM IF), data in the main data region of CHIP1(FLASH3) is directly transferred to the copy region of CHIP3 (DRAM3).When a store instruction is written to the control register DREG, datain the copy region of CHIP3 (DRAM3) is directly written to the main dataregion of CHIP1 (FLASH3).

When an instruction to read CHIP1 (FLASH3) data held in the memory bank0 (B0) of CHIP3 (DRAM3) and an address are input from the informationprocessing device CHIP4 (MS) via the SDRAM interface (SDRAM IF), theaccess arbiter ARB always precedes the read instruction from theinformation processing device CHIP4 (MS) and if data transfer betweenCHIP1 (FLASH3) and CHIP3 (DRAM3) is performedby a load instruction or astore instruction, the access arbiter stops it. Afterward, the commanddecoder CDEC decodes the read instruction, reads the data from thememory bank 0 (B0), and outputs it via the SDRAM interface.

In case an AND interface (AND IF) is used for data transfer betweenCHIP1 (FLASH3) and CHIP3 (DRAM3) in this memory module MM3, it needscarcely be said that this memory module can be also implemented.

As described above, in this embodiment, as SRAM, the error detecting andcorrecting circuit ECC and the address replacement circuit REP are builtin CHIP1 (FLASH3), data transfer between the non-volatile memory arrayand SRAM can be performed at high speed.

As CHIP3 (DRAM3) is provided with the SDRAM interface (SDRAM IF) and theNAND interface (NAND IF), the NAND interface (NAND IF) can be directlyconnected to CHIP1 (FLASH3) and the SDRAM interface (SDRAM IF) can bedirectly connected to the information processing device CHIP4 (MS), datacan be read at higher speed.

Further, as the number of chips for implementing this memory system canbe reduced, the power and the cost can be reduced.

Fifth Embodiment

FIG. 22 shows a fifth embodiment to which the invention is applied. FIG.22 shows an embodiment of an information processing system configured bya memory module MM4 and an information processing device CHIP4 (MS).Each will be described below.

The memory module MM4 is configured by CHIP1 (FLASH4) and CHIP3 (DRAM4).CHIP1 (FLASH4) is a non-volatile memory and is a large-capacity flashmemory equipped with a NAND interface (NAND IF) though theabove-mentioned is not particularly limited.

CHIP1 (FLASH4) is configured by a non-volatile memory array MA forholding data, a transfer control circuit FCTL4, an error detecting andcorrecting circuit ECC and an address replacement circuit REP.

As for the configuration of the memory array MA, there are mainly NANDconfiguration and AND configuration and both can be used.

CHIP3 (DRAM4) is DRAM equipped with an interface for data transferto/from CHIP1 (FLASH4) and an interface for data transfer to/from theinformation processing device CHIP4 (MS).

The interface for data transfer to/from the information processingdevice CHIP4 (MS) has two types of an asynchronous DRAM interface and asynchronous DRAM interface and both interfaces can be used in the memorymodule MM4. This embodiment will be described using an SDRAM interface(SDRAM IF) which is the synchronous DRAM interface typically used for anexample.

The interface for data transfer between CHIP3 (DRAM4) and CHIP1 (FLASH4)is a flash memory interface, the flash memory interface has two types ofan AND interface (AND IF) and a NAND interface (NAND IF), and in thisembodiment, both can be used. This embodiment will be described usingthe NAND interface for the interface for data transfer between CHIP3(DRAM4) and CHIP1 (FLASH4) below.

Next, the configuration of CHIP3 (DRAM4) will be described. CHIP3(DRAM4) is configured by memory banks (B0, B1, B2, B3) for holding dataand a control circuit DCTL4 for controlling reading and writing datafrom/to the memory bank. The control circuit DCTL4 is configured by acommand decoder CDEC, an access arbiter ARB, a memory management unitDMU, an initialize circuit INT, a refresh control circuit REF, a databuffer BUF, a control register DREG, a mode register MR, an extendedmode register EMR, a flash control circuit DFCON and SRAM.

By the memory management unit DMU, CHIP1 (FLASH4) is divided into aninitial program region and a main data region though the above-mentionedis not particularly limited, CHIP3 (DRAM4) is divided into a work regionand a copy region though the above-mentioned is not particularlylimited, and is managed so that the work region is used for a workmemory when a program is executed and the copy region is used for amemory for copying data from FLASH. The memory banks B0 and B1 of CHIP3(DRAM4) can be also allocated to the copy region and the memory banks B2and B3 can be also allocated to the work region.

Further, SRAM is divided into a boot program region and a buffer regionand is managed so that the boot program region is used for storing bootprogram data for activating the information processing device CHIP4 (MS)and the buffer region is used for a buffer memory for data transferbetween the non-volatile memory array MA of CHIP1 (FLASH4) and SRAM.

The information processing device CHIP4 (MS) is configured by a centralprocessing unit CPU, an SRAM controller SRC and a DRAM controller SDC.The DRAM controller accesses SRAM of CHIP3 (DRAM4) and the memory banks(B0, B1, B2, B3) via the SDRAM interface (SDRAM IF) to read or writedata.

As described above, in this embodiment, as the error detecting andcorrecting circuit ECC and the address replacement circuit REP are builtin CHIP1 (FLASH4), error detection and error correction in reading datacan be made at high speed and the replacement of an address in writingdata can be also made at high speed, data transfer can be sped up.

As CHIP3 (DRAM4) is provided with the SDRAM interface (SDRAM. IF) andthe NAND interface (NAND IF), the NAND interface (NAND IF) can bedirectly connected to CHIP1 (FLASH4) and the SDRAM interface (SDRAM IF)can be directly connected to the information processing device CHIP4(MS), data can be read at higher speed.

As the number of chips for implementing this memory system can bereduced, the power and the cost can be reduced.

Further, as this memory system is operated only via the SDRAM interface,terminals for connection to the information processing device CHIP4 (MS)can be reduced, and the power and the cost can be further reduced.

Next, the operation of this embodiment will be described.

When power is turned on, CHIP1 (FLASH4) and CHIP3 (DRAM4) set themselvesto an initial condition.

Next, the flash control circuit DFCON reads data in the initial programregion of the non-volatile memory array MA and transfers it to the bootprogram region of SRAM.

When data is read from the non-volatile memory array MA of CHIP1(FLASH4), an error in the data is detected and corrected at high speedby the built-in error detecting and correcting circuit ECC.

The information processing device CHIP4 (MS) reads boot program datastored in the boot program region of SRAM via the SDRAM interface (SDRAMIF) and activates itself.

The initialize circuit INT sets the mode register MR and the extendedmode register EMR to a desired value as a sequence for initializingCHIP3 (DRAM4).

Next, the flash control circuit DFCON of CHIP3 (DRAM4) sequentiallyreads data in the main data region of the non-volatile memory array MAvia the transfer control circuit FCTL4 and transfers it to the databuffer BUF. The command decoder CDEC sequentially transfers the dataheld in the data buffer BUF to the memory bank 0 (B0) allocated to thecopy region. When data transfer is started, the refresh control circuitREF executes refresh operation to hold the data transferred to thememory bank 0 (B0).

When a load instruction is written to a control register SREG of CHIP3(DRAM4) from the information processing device CHIP4 (MS) via the SDRAMinterface (SDRAM IF), data in the main data region held the non-volatilememory array MA is transferred to the buffer region of SRAM. When astore instruction is written to the control register SREG, the data inthe buffer region of SRAM is transferred to the main data region of thenon-volatile memory array MA.

When data is written to the non-volatile memory array MA, it is checkedat high speed by the built-in address replacement circuit REP whetherthe writing succeeds or not, if the writing succeeds, it is finished,when the wiring fails, an address in an address replacement region FREPof CHIP1 (FLASH4) is selected and the data is written.

When a load instruction is written to the control register DREG of CHIP3(DRAM4) from the information processing device CHIP4 (MS) via the SDRAMinterface (SDRAM IF), data in the main data region of CHIP1 (FLASH4) istransferred to the copy region of CHIP3 (DRAM4). When a storeinstruction is written to the control register DREG, data in the copyregion of CHIP3 (DRAM4) is directly written to the main data region ofCHIP1 (FLASH4).

When an instruction to read CHIP1 (FLASH4) data held in the memory bank0 (B0) of CHIP3 (DRAM4) and an address are input from the informationprocessing device CHIP4 (MS) via the SDRAM interface (SDRAM IF), theaccess arbiter ARB always precedes the read instruction from theinformation processing device CHIP4 (MS) and if data transfer isperformed between CHIP1 (FLASH4) and CHIP3 (DRAM4) by a load instructionor a store instruction, the access arbiter stops it. Afterward, thecommand decoder CDEC decodes the read instruction, reads data in thememory bank 0 (B0), and outputs it via the SDRAM interface.

In case an AND interface (AND IF) is used for data transfer betweenCHIP1 (FLASH4) and CHIP3 (DRAM4) in this memory module MM4, it needscarcely be said that this memory module can be also implemented.

As described above, in this embodiment, as the error detecting andcorrecting circuit ECC and the address replacement circuit REP are builtin CHIP1 (FLASH4), an error can be detected and corrected at high speedin reading data and as the replacement of an address in writing data canbe also made at high speed, data transfer can be sped up.

As CHIP3 (DRAM4) is provided with the SDRAM interface (SDRAM IF) and theNAND interface (NAND IF), the NAND interface (NAND IF) can be directlyconnected to CHIP1 (FLASH4) and the SDRAM interface (SDRAM IF) can bedirectly connected to the information processing device CHIP4 (MS), datacan be read at higher speed.

As the number of chips for implementing this memory system can bereduced, the power and the cost can be reduced.

Further, as this memory system is operated only via the SDRAM interface,terminals for connection to the information processing device CHIP4 (MS)can be reduced, and the power and the cost can be further reduced.

FIG. 23 shows one example of a memory map by the memory management unitDMU in this embodiment. In this embodiment, though the following are notparticularly limited, a representative memory map will be describedusing a memory module where a memory area of the non-volatile memory is128 Mbits+4 Mbits (4 Mbits are an address replacement region), a memoryarea of DRAMis 256 Mbits, SRAM is 8 kbits and the control registers SREGand DREG are 1 kbits for an example below.

There is shown a memory map showing that the memory management unit DMUconverts to an address in the control register DREG (1 kb), the workregion WK (128 Mbits) of DRAM, the copy region CP (128 Mbits) of DRAM,the control register SREG, SRAM and Flash (128 Mbits) based upon anaddress input via the SDRAM interface (SDRAM IF).

Though the following is not particularly limited, SRAM, the controlregister SREG, the bank 0 (BANK0), the bank 1 (BANK1), the bank 2(BANK2) and the bank 3 (BANK3) respectively of DRAM and the controlregister DREG are mapped from a lower part of address space of thememory map.

SRAM is divided into the boot program region SBoot and a buffer regionSBUF.

The bank 0 (BANK0) and the bank 1 (BANK1) of DRAM are mapped in the copyregion CP, and the bank 2 (BANK2) and the bank 3 (BANK3) are mapped inthe work region WK. The copy region CP is a region to/in which data inFLASH is transferred and held. The work region WK is a region used for awork memory. An initial automatic data transfer region CIP is includedin the copy region CP of the bank 1 (BANK1).

FLASH is divided into the main data region FM, the initial programregion FBoot and the address replacement region FREP. An initialautomatic data transfer region IP from which data is automaticallytransferred to DRAM when power is turned on is included in the main dataregion FM of FLASH.

In the main data region FM of FLASH, a program and data are stored.There occurs, though infrequently, that the reliability of FLASH isdeteriorated by repeating writing, written data may be turned to bedifferent data in reading, and in writing, no data is written. Theaddress replacement region FREP is provided to reload data turneddefective as described above in the initial program region FBoot and inthe main data region FM into a new region. The size of the addressreplacement region is not particularly limited, however, it is desirablethat the size is determined so that the reliability which FLASHguarantees can be secured.

After power is turned on, first, data in the initial program regionFBoot of FLASH is transferred to the boot program region SBoot of SRAM.The information processing device CHIP4 (MS) reads the data in the bootprogram region SBoot of SRAM via the SDRAM interface (SDRAM IF) andactivates itself.

Next, data in the initial automatic data transfer region IP of FLASH istransferred to the initial automatic data transfer region CIP of DRAM.

Data transfer from FLASH to DRAM according to a load instruction (Load)will be described below.

When the load instruction is written to the control register DREG viathe SDRAM interface (SDRAM IF), data in the main data region of FLASH istransferred to the copy region of DRAM according to the memory map setby the memory management unit MU.

Data transfer from DRAM to FLASH according to a store instruction(Store) will be described below.

When the store instruction is written to the control register DREG viathe SDRAM interface (SDRAM IF), data in the copy region of DRAM istransferred to the main data region of FLASH according to the memory mapset by the memory management unit MU.

Next, reading data from DRAM will be described.

When an address of the bank 0 (BANK0) of DRAM and a read instruction areinput via the SDRAM interface, an address in the bank 0 (BANK0) of DRAMis selected and data can be read from there. That is, data in FLASH canbe read at the same speed as that in DRAM. Data can be similarly readfrom other banks (the bank 1, the bank 2 and the bank 3).

Next, writing data to DRAM will be described.

When an address of the bank 1 (BANK1) of DRAM and a write instructionare input via the SDRAM interface, an address in the bank 1 (BANK1) ofDRAM is selected and data can be written there. That is, data in FLASHcan be written at the same speed as that in DRAM. Data can be similarlywritten to other banks (the bank 3, the bank 2 and the bank 0).

Data transfer from FLASH to SRAM according to a load instruction will bedescribed below.

When the load instruction (SLoad) is written to the control registerSREG via the SDRAM interface (SDRAM. IF), data in FLASH is transferredto the buffer region of SRAM according to the memory map set by thememory management unit DMU.

Data transfer from SRAM to FLASH according to a store instruction(SStore) will be described below.

When the store instruction is written to the control register SREG viathe SDRAM interface (SDRAM IF), data in the buffer region of SRAM istransferred to FLASH according to the memory map set by the memorymanagement unit DMU.

Next, reading data from SRAM will be described.

When an address for selecting SRAM and a read instruction are input viathe SDRAM interface, SRAM is selected and data can be read from there.

Next, writing data to SRAM will be described.

When an address for selecting SRAM and a write instruction are input viathe SDRAM interface, SRAM is selected and data can be written there.

As described above, all data transfer is performed via the SDRAMinterface (SDRAM IF).

Sixth Embodiment

FIG. 24 shows a sixth embodiment to which the invention is applied. FIG.24 shows an embodiment of a memory system configured by a memory moduleMM5 and an information processing device CHIP4 (MS). Each will bedescribed below.

The memory module MM5 is configured by CHIP1 (FLASH4), CHIP2 (DRAM4) andCHIP3 (DRAM4). CHIP1 (FLASH4) is the similar memory to the non-volatilememory shown in FIG. 22 and is provided with a NAND interface (NAND IF).

CHIP2 (DRAM4) and CHIP3 (DRAM4) are the same DRAM and are DRAM acquiredby adding a master selection signal MSL to DRAM shown in FIG. 22. DFCONdenotes a flash control circuit for controlling data transfer to/fromCHIP1 (FLASH4).

This memory module MM5 uses two DRAMs to increase the memory size ofDRAM.

Data transfer between CHIP2 (DRAM4) or CHIP3 (DRAM4) and CHIP1 (FLASH4)is performed via the NAND interface (NAND IF) and data transfer betweenCHIP2 (DRAM4) or CHIP3 (DRAM4) and the information processing deviceCHIP4 (MS) is performed via the SDRAM interface (SDRAM IF).

The master selection signal MSL is a signal for selecting which of CHIP2(DRAM4) or CHIP3 (DRAM4) mainly accesses CHIP1 (FLASH4).

In CHIP2 (DRAM4), a master selection signal line MSL is connected to apower supply terminal VDD and CHIP2 becomes master DRAM thatindependently accesses CHIP1 (FLASH4). In CHIP3 (DRAM4), the masterselection signal line MSL is connected to an earth terminal VSS (0 V)and CHIP3 becomes slave DRAM that does not independently access CHIP1(FLASH4).

In CHIP2 (DRAM4) as master DRAM, the flash control circuit DFCON issuesa control signal to enable data transfer to/from CHIP1 (FLASH4).

In CHIP3 (DRAM4) as slave DRAM, the flash control circuit DFCON in CHIP2(DRAM4) does not issue a control signal and data for data transferto/from CHIP1 (FLASH4) and performs data transfer to/from CHIP1 (FLASH4)using a control signal issued by the flash control circuit DFCON ofCHIP2 (DRAM4).

In case there are plural master DRAMs that independently access theflash memory, control signals to the flash memory are in a competitivesituation, data transfer between the flash memory and DRAM fails, and itis difficult to increase memory size using plural DRAM chips. Accordingto this embodiment, as master DRAM and slave DRAM can be selected byissuing the master selection signal MSL and the memory size can beincreased using the plural DRAM chips, the invention can flexiblycorrespond to a request of a mobile device.

Seventh Embodiment

FIG. 25( a) and FIG. 25( b) show a seventh embodiment in the invention.FIG. 25( a) is a top view and FIG. 25( b) is a sectional view showing apart viewed along a line A-A′ shown in the top view.

As for a multichip module equivalent to this embodiment, CHIPM1 andCHIPM2 are mounted on a board for mounting the devices with a ball gridarray (BGA) (for example, a printed circuit board made of glass epoxy)PCB. CHIPM1 is a non-volatile memory and CHIPM2 is DRAM. The memorymodule MM3 shown in FIG. 21 and the memory module MM4 shown in FIG. 22can be integrated in one molded device by this multichip module.

CHIPM1 and a bonding pad on the board PCB are connected via bonding wire(PATH2), and CHIPM2 and a bonding pad on the board PCB are connected viabonding wire (PATH1). CHIPM1 and CHIPM2 are connected via bonding wire(PATH3).

The top face of the board PCB on which the chips are mounted is resinmolded to protect each chip and wiring for connection. Further, a cover(COVER) made of metal, a ceramic or resin may also cover them.

In this embodiment, as the bare chip is directly mounted on the printedcircuit board PCB, the memory module having small packaging area can beconfigured. Besides, as each chip can be laminated, wiring lengthbetween the chip and the board PCB can be reduced and the packaging areacan be reduced. The memory module can be manufactured with a smallnumber of processes by unifying wiring between the chips and wiringbetween each chip and the board in a method using bonding wire.

Further, the number of bonding pads on the board and the number ofbonding wires are reduced by directly connecting the chips via bondingwire and the memory module can be manufactured with a small number ofprocesses. In case the cover made of resin is used, the tougher memorymodule can be configured. In case the cover made of a ceramic or metalis used, the memory module excellent in the performance of outgoingradiation and the effect of shielding in addition to the strength can beconfigured.

Eighth Embodiment

FIG. 26( a) and FIG. 26( b) show an eighth embodiment in the invention.FIG. 26( a) is a top view and FIG. 26( b) is a sectional view showing apart viewed along a line A-A′ shown in the top view.

As for a multichip module equivalent to this embodiment, CHIPM1, CHIPM2and CHIPM3 are mounted on a board for mounting the devices with a ballgrid array (BGA) (for example, a printed circuit boardmade of glassepoxy) PCB. CHIPM1 is a non-volatile memory and CHIPM2 is DRAM. CHIPM3is an information processing device configured by a central processingunit CPU, an SRAM controller SRC and a DRAM controller SDC or a controlcircuit for controlling data transfer between CHIPM1 and CHIPM2.

The memory module MM shown in FIG. 1, the memory module MM shown in FIG.14, the memory module MM1 shown in FIG. 17, the memory module MM2 shownin FIG. 18, the memory system shown in FIG. 21 and the memory systemshown in FIG. 22 can be integrated in one molded device by thismultichip module.

CHIPM1 and a bonding pad on the board PCB are connected via bonding wire(PATH2), and CHIPM2 and a bonding pad on the board PCB are connected viabonding wire (PATH1). CHIPM1 and CHIPM2 are connected via bonding wire(PATH3). The ball grid array is used for mounting and wiring CHIPM3.

As the three chips can be laminated in the mounting method in thisembodiment, packaging area can be kept small. Further, as bondingbetween CHIPM3 and the board is not required and the number of bondingwires can be reduced, manhours required for assembly can be reduced andin addition, the more reliable multichip module can be implemented.

Ninth Embodiment

FIG. 27( a) and FIG. 27( b) show a ninth embodiment of the multichipmodule according to the invention. FIG. 27( a) is a top view and FIG.27( b) is a sectional view showing a part viewed along a line A-A′ shownin the top view.

As for a memory module equivalent to this embodiment, CHIPM1, CHIPM2,CHIPM3 and CHIPM4 are mounted on a board for mounting the devices with aball grid array (BGA) (for example, a printed circuit board made ofglass epoxy) PCB. CHIPM1 is a non-volatile memory and CHIPM3 is DRAM.CHIPM2 is a control circuit for controlling data transfer between CHIPM1and CHIPM2 and CHIPM4 is an information processing device configured bya central processing unit CPU, an SRAM controller SRC and a DRAMcontroller SDC.

In the mounting method in this embodiment, the memory system shown inFIG. 1, the memory system module shown in FIG. 14, the memory systemshown in FIG. 17 and the memory system shown in FIG. 18 can beintegrated in one molded device.

CHIPM1 and a bonding pad on the board PCB are connected via bonding wire(PATH2), CHIPM2 and a bonding pad on the board PCB are connected viabonding wire (PATH1), and CHIPM3 and a bonding pad on the board PCB areconnected via bonding wire (PATH4).

CHIPM1 and CHIPM2 are connected via bonding wire (PATH3), and CHIPM2 andCHIPM3 are connected via bonding wire (PATH5).

The ball grid array (BGA) is used for mounting and wiring CHIPM4.

As the bare chips are directly mounted on the printed circuit board PCBin the mounting method in this embodiment, the memory module havingsmall packaging area can be configured. Besides, as each chip can beclosely arranged, wiring length between the chips can be reduced.

The number of bonding pads on the board and the number of bonding wiresare reduced by directly wiring the chips via the bonding wire and thememory module can be manufactured with small processes.

Further, as bonding between CHIPM4 and the board is not required and thenumber of bonding wires can be reduced, manhours for assembly can bereduced and in addition, the more reliable multichip module can beimplemented.

Tenth Embodiment

FIG. 28( a) and FIG. 28( b) show a tenth embodiment of the memory systemaccording to the invention. FIG. 28( a) is a top view and FIG. 28( b) isa sectional view showing a part viewed along a line A-A′ shown in thetop view.

As for a memory module equivalent to this embodiment, CHIPM1, CHIPM2 andCHIPM3 are mounted on a board for mounting the devices with a ball gridarray (BGA) (for example, a printed circuit boardmade of glass epoxy)PCB. CHIPM1 is a non-volatile memory, and CHIPM2 and CHIPM3 are DRAM.The memory module can be manufactured with small processes by unifyingwiring between the chips and wiring between each chip and the board in amethod using bonding wire.

In the mounting method in this embodiment, the module MM5 shown in FIG.24 can be integrated in one molded device.

CHIPM1 and a bonding pad on the board PCB are connected via bonding wire(PATH2), CHIPM2 and a bonding pad on the board PCB are connected viabonding wire (PATH1), and CHIPM3 and a bonding pad on the board PCB areconnected via bonding wire (PATH3).

In this embodiment, as the bare chips are directly mounted on theprinted circuit board PCB, the memory module having small packaging areacan be configured.

Besides, as each chip can be closely arranged, wiring length between thechips can be reduced.

The memory module can be manufactured with small processes by unifyingwiring between each chip and the board in a method using bonding wire.

Eleventh Embodiment

FIG. 29( a) and FIG. 29( b) show an eleventh embodiment of the memorysystem according to the invention. FIG. 29( a) is a top view and FIG.29( b) is a sectional view showing a part viewed along a line A-A′ shownin the top view.

As for a memory module equivalent to this embodiment, CHIPM1, CHIPM2,CHIPM3 and CHIPM4 are mounted on a board for mounting the devices with aball grid array (BGA) (for example, a printed circuit board made ofglass epoxy) PCB. CHIPM1 is a non-volatile memory, and CHIPM2 and CHIPM3are DRAM. CHIPM4 is an information processing device configured by acentral processing unit CPU, an SRAM controller SRC and a DRAMcontroller SDC.

In this multichip module, the memory system shown in FIG. 24 can beintegrated in one molded device.

CHIPM1 and a bonding pad on the board PCB are connected via bonding wire(PATH2), CHIPM2 and a bonding pad on the board PCB are connected viabonding wire (PATH1), and CHIPM3 and a bonding pad on the board PCB areconnected via bonding wire (PATH3).

The ball grid array (BGA) is used for mounting and wiring CHIPM4.

In this embodiment, as the bare chips are directly mounted on theprinted circuit board PCB, the memory module having small packaging areacan be configured. Besides, as each chip can be closely arranged, wiringlength between the chips can be reduced. As bonding between CHIPM4 andthe board is not required and the number of bonding wires can bereduced, manhours required for assembly can be reduced and in addition,a more reliable multichip module can be implemented.

Twelfth Embodiment

FIG. 30 shows a twelfth embodiment showing a mobile telephone utilizingthe memory module according to the invention. The mobile telephone isconfigured by an antenna ANT, a wireless block RF, a base-band block BB,a voice codec block SP, a speaker SK, a microphone MK, a processor CPU,a liquid crystal display block LCD, a keyboard KEY and the memory moduleMEM according to the invention.

The operation in a call will be described below.

Voice received via the antenna ANT is amplified in the wireless block RFand is input to the base-band block BB. In the base-bandblock BB, ananalog signal of the voice is converted to a digital signal, errorcorrection and decoding are performed, and the digital signal is outputto the voice codec block SP. When the voice codec block converts thedigital signal to an analog signal and outputs it to the speaker SK, thevoice of a partner can be heard from the speaker.

The operation when a series of work that a home page of the Internet isaccessed from the mobile telephone, music data is downloaded, isreproduced andheard and finally the downloaded music data is stored isperformed will be described below.

In the memory module MEM, a basic program and an application program fora mail, for reproducing music and for a game such as a web browser arestored.

When the activation of the web browser is instructed via the keyboard, aprogram of the web browser stored in FLASH in the memory module MEM istransferred to DRAM in the same memory module. When data transfer toDRAM is finished, the processor CPU executes the program of the webbrowser in DRAM and instructs the liquid crystal display block LCD todisplay the web browser. When a desired home page is accessed and thedownload of desired music data is instructed via the keyboard KEY, themusic data is received via the antenna ANT, is amplified in the wirelessblock RF, and is input to the baseband block BB. In the baseband blockBB, the music data which is an analog signal is converted to a digitalsignal, and error correction and decoding are performed. Finally, thedigitized music data is once stored in DRAM of the memory module MEM andis transferred to FLASH.

Next, when the activation of a music reproduction program is instructedvia the keyboard KEY, the music reproduction program stored in FLASH inthe memory module MEM is transferred to DRAM in the same memory module.When the data transfer to DRAM is finished, the processor CPU executesthe music reproduction program in DRAM and instructs the liquid crystaldisplay block LCD to display the music reproduction program.

When an instruction to listen to music data downloaded into DRAM is madevia the keyboard KEY, the processor CPU executes a music reproductionprogram, processes the music data held in DRAM, and finally music can beheard from the speaker SK.

At this time, as the memory module according to the invention useslarge-capacity DRAM, a web browser and the music reproduction programare held in DRAM and both programs are simultaneously executed by CPU.Further, an electronic mail program is activated, and the execution ofthe electronic mail program and the transmission/reception of a mail arealso simultaneously enabled.

As a web browser is held in DRAM in the memory module even if the webbrowser is stopped, it can be promptly activated in reactivation.

When an instruction to turn off power is input via the keyboard, thememory module instructs so that only SRAM is operated, holds data at theminimum, and enables the extreme minimization of power consumption.

As described above, a large quantity of mails, reproduced music,application programs, music data, static image data and dynamic imagedata can be stored by using the memory module according to theinvention, and further, plural programs can be simultaneously executed.

Thirteenth Embodiment

FIG. 31 shows a thirteenth embodiment showing a mobile telephoneutilizing the memory system according to the invention. The mobiletelephone is configured by an antenna ANT, a wireless block RF, abase-band block BB, a voice codec block SP, a speaker SK, a microphoneMK, a liquid crystal display block LCD, a keyboard KEY and the memorysystem SL according to the invention in which a processor CPU and thememory module MEM are integrated in one molded device.

As the number of parts can be reduced by using the memory system SLaccording to the invention, the cost can be reduced, the reliability ofthe mobile telephone is enhanced, the packaging area of partsconfiguring the mobile telephone can be reduced, and the mobiletelephone can be small-sized.

INDUSTRIAL APPLICABILITY

As described above, effect acquired by the invention is as follows.

First, the mobile device can read a boot program in SRAM and canpromptly activate itself by automatically transferring the boot programfrom FLASH to SRAM when power is turned on.

Second, as this memory module can be accessed promptly when the mobiledevice is activated by automatically transferring a program requiredwhen power is turned on from FLASH to DRAM, the performance of themobile device can be enhanced.

Third, in the memory module to which the memory system according to theinvention is applied, data in FLASH can be read and written at thesimilar speed to that of data in DRAM by securing a region in which apart of data or the whole data in FLASH can be copied in DRAM andtransferring data from FLASH to the region in DRAM in advance.

Fourthly, inside this memory module, as the detection and the correctionof an error are performed in reading from FLASH and a defective addressat which writing is not correctly performed is replaced in writing,high-speed processing is enabled and reliability can be kept.

Fifthly, as large-capacity DRAM is used in this memory module, alarge-capacity work region can be also secured in addition to a regionin which data in FLASH can be copied and the memory module cancorrespond to the enhancement of the function of the mobile telephone.

Sixthly, even if data is being transferred between FLASH and DRAMaccording to a load instruction or a store instruction inside thismemory module, access from a device outside the memory module to DRAM isenabled without being conscious of the data transfer and the memorymodule can correspond to the enhancement of the performance and thefunction of the mobile device.

Seventhly, as inside the memory module, automatic refresh is performedsince the transfer of an initial program from FLASH to DRAM after poweris turned on is started until an automatic refresh instruction is inputfrom a device outside the memory module, the switching of refreshcontrol can be promptly and precisely made.

Besides, data in DRAM can be held with small power until an instructionto release a self-refresh condition is input from a device outside thememory module by turning DRAM a self-refresh condition after thetransfer of an initial program from FLASH to DRAM after power is turnedon is finished.

Eighthly, as boot program data and designation data for the automaticdata transfer region can be written to the initial program region ofFLASH via the SRAM interface which is a general interface and the bootmethod and the data transfer region immediately after power is turned oncan be changed, the invention can flexibly correspond to a request ofthe mobile device and the function can be enhanced.

Ninthly, the system memory module having small packaging area can beprovided by integrating plural semiconductor chips in one molded device.

1-78. (canceled)
 79. A mobile telephone comprising: an antenna; awireless block coupled to the antenna; a base-band block coupled to thewireless block; a voice codec block coupled to the base-band block; aspeaker coupled to the voice codec block; a microphone coupled to thevoice codec block; a display block coupled to the base-band block; and amemory system including a memory module having a non-volatile memory, adynamic random access memory, a static random access memory, and a firstcontrol circuit that accesses the non-volatile memory, the dynamicrandom access memory, and the static random access memory, wherein thememory module comprises a dynamic random access memory interface foraccessing, from a device outside the memory module, the dynamic randomaccess memory and the static random access memory, and wherein thedynamic random access memory includes plural interfaces for accessingplural memories.
 80. The mobile telephone according to claim 79, whereinthe plural interfaces are for accessing at least two types of differentmemories.
 81. The mobile telephone according to claim 80, wherein,immediately after power is turned on, data in a predetermined addressregion of the non-volatile memory is transferred to the static randomaccess memory.
 82. The mobile telephone according to claim 80, wherein,immediately after power is turned on, data in a predetermined addressregion of the non-volatile memory is transferred to the dynamic randomaccess memory.
 83. The mobile telephone according to claim 80, whereindata transfer between the non-volatile memory and the dynamic randomaccess memory or the static random access memory is performed based onan instruction sent via the dynamic random access memory interface. 84.The mobile telephone according to claim 80, wherein, in transferringdata from the non-volatile memory to the static random access memory orthe dynamic random access memory, data acquired by correcting an erroris transferred.
 85. The mobile telephone according to claim 80, wherein,in transferring data from the static random access memory or the dynamicrandom access memory to the non-volatile memory, an address replacementprocess is executed.
 86. The mobile telephone according to claim 80,wherein a boot program is held in the non-volatile memory.
 87. Themobile telephone according to claim 80, wherein data transfer rangedata, which includes a range of data transferred from the non-volatilememory to the dynamic random access memory at initial time whenoperating power is turned on, is held in the non-volatile memory. 88.The mobile telephone according to claim 80, wherein the non-volatilememory and the dynamic random access memory are similar in memory size,and wherein the static random access memory has a memory size equal toor smaller than 1/1000 of the memory size of the non-volatile memory.89. The mobile telephone according to claim 82, wherein data transferrange data, which includes a range of a predetermined address region ofthe non-volatile memory, is held in the non-volatile memory.
 90. Themobile telephone according to claim 80, wherein a data-hold operation ofthe dynamic random access memory is executed inside the memory module.91. The mobile telephone according to claim 90, wherein, when thedata-hold operation is provided to the dynamic random access memory fromthe device, the data-hold operation of the dynamic random access memoryinside the memory module is stopped.
 92. The mobile telephone accordingto claim 80, wherein: the device accesses the memory module first; thedynamic random access memory performs a data-hold operation second; andthe memory module performs data transfer between the non-volatile memoryand the static random access memory or the dynamic random access memorythird.
 93. The mobile telephone according to claim 80, wherein thedynamic random access memory is synchronous, and wherein access to thenon-volatile memory and the dynamic random access memory from the deviceis made via the dynamic random memory access interface.
 94. The mobiletelephone according to claim 80, wherein the non-volatile memory is aNAND flash memory, and wherein the dynamic random access memory issynchronous.
 95. The mobile telephone according to claim 80, wherein thenon-volatile memory is an AND flash memory, and wherein the dynamicrandom access memory is synchronous.
 96. The mobile telephone accordingto claim 80, wherein the non-volatile memory performs error detection,error correction, and address replacement.
 97. The mobile telephoneaccording to claim 96, wherein a memory array of the non-volatile memoryis configured according to NAND configuration.
 98. The mobile telephoneaccording to claim 96, wherein a memory array of the non-volatile memoryis configured according to AND configuration.
 99. The mobile telephoneaccording to claim 80, wherein the dynamic random access memory includesa second control circuit which processes access from the device and athird control circuit that independently accesses the non-volatilememory.
 100. The mobile telephone according to claim 80, wherein thedynamic random access memory includes a second control circuit thatindependently accesses the non-volatile memory and a circuit tosubordinately process access to the non-volatile memory by the secondcontrol circuit.
 101. The mobile telephone according to claim 79,wherein the plural interfaces are for accessing the dynamic randomaccess memory and the non-volatile memory.
 102. The mobile telephoneaccording to claim 101, wherein, immediately after power is turned on,data in a predetermined address region of the non-volatile memory istransferred to the static random access memory.
 103. The mobiletelephone according to claim 101, wherein, immediately after power isturned on, data in a predetermined address region of the non-volatilememory is transferred to the dynamic random access memory.
 104. Themobile telephone according to claim 101, wherein data transfer betweenthe non-volatile memory and the dynamic random access memory or thestatic random access memory is performed based on an instruction sentvia the dynamic random access memory interface.
 105. The mobiletelephone according to claim 101, wherein, in transferring data from thenon-volatile memory to the static random access memory or the dynamicrandom access memory, data acquired by correcting an error istransferred.
 106. The mobile telephone according to claim 101, wherein,in transferring data from the static random access memory or the dynamicrandom access memory to the non-volatile memory, an address replacementprocess is executed.
 107. The mobile telephone according to claim 101,wherein a boot program is held in the non-volatile memory.
 108. Themobile telephone according to claim 101, wherein data transfer rangedata, which includes a range of data transferred from the non-volatilememory to the dynamic random access memory at initial time whenoperating power is turned on, is held in the non-volatile memory. 109.The mobile telephone according to claim 101, wherein the non-volatilememory and the dynamic random access memory are similar in memory size,and wherein the static random access memory has a memory size equal toor smaller than 1/1000 of the memory size of the non-volatile memory.110. The mobile telephone according to claim 103, wherein data transferrange data, which includes a range of a predetermined address region ofthe non-volatile memory, is held in the non-volatile memory.
 111. Themobile telephone according to claim 101, wherein a data-hold operationof the dynamic random access memory is executed inside the memorymodule.
 112. The mobile telephone according to claim 111, wherein, whenthe data-hold operation is provided to the dynamic random access memoryfrom the device, the data-hold operation of the dynamic random accessmemory inside the memory module is stopped.
 113. The mobile telephoneaccording to claim 101, wherein: the device accesses the memory modulefirst; the dynamic random access memory performs a data-hold operationsecond; and the memory module performs data transfer between thenon-volatile memory and the static random access memory or the dynamicrandom access memory third.
 114. The mobile telephone according to claim101, wherein the dynamic random access memory is synchronous, andwherein access to the non-volatile memory and the dynamic random accessmemory from the device is made via the dynamic random memory accessinterface.
 115. The mobile telephone according to claim 101, wherein thenon-volatile memory is a NAND flash memory, and wherein the dynamicrandom access memory is synchronous.
 116. The mobile telephone accordingto claim 101, wherein the non-volatile memory is an AND flash memory,and wherein the dynamic random access memory is synchronous.
 117. Themobile telephone according to claim 101, wherein the non-volatile memoryperforms error detection, error correction, and address replacement.118. The mobile telephone according to claim 117, wherein a memory arrayof the non-volatile memory is configured according to NANDconfiguration.
 119. The mobile telephone according to claim 117, whereina memory array of the non-volatile memory is configured according to ANDconfiguration.
 120. The mobile telephone according to claim 101, whereinthe dynamic random access memory includes a second control circuit whichprocesses access from the device and a third control circuit thatindependently accesses the non-volatile memory.
 121. The mobiletelephone according to claim 101, wherein the dynamic random accessmemory includes a second control circuit that independently accesses thenon-volatile memory and a circuit to subordinately process access to thenon-volatile memory by the second control circuit.